Texas Instruments TMS320C6712D General-purpose input/output Gpio, GP7 GP6 GP5 GP4 GP2, Dir

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

general-purpose input/output (GPIO)

To use the GP[7:4, 2] software-configurable GPIO pins, the GPxEN bits in the GP Enable (GPEN) Register and the GPxDIR bits in the GP Direction (GPDIR) Register must be properly configured.

GPxEN =

1

GP[x] pin is enabled

GPxDIR =

0

GP[x] pin is an input

GPxDIR =

1

GP[x] pin is an output

where “x” represents one of the 7 through 4, or 2 GPIO pins

Figure 9 shows the GPIO enable bits in the GPEN register for the device. To use any of the GPx pins as general-purpose input/output functions, the corresponding GPxEN bit must be set to “1” (enabled). Default values are device-specific, so refer to Figure 9 for the default configuration.

31

 

 

 

 

 

 

 

24

23

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

 

 

 

 

15

14

13

12

 

11

10

9

8

 

6

5

4

 

3

2

1

0

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GP7

GP6

GP5

GP4

 

 

GP2

 

 

 

 

 

Reserved

 

 

 

EN

EN

EN

EN

 

—

EN

—

—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W-0

 

 

 

 

R/W-1

R/W-1

R/W-1

R/W-1

 

R/W-0

R/W-0

R/W-0

R/W-0

Legend: R/W = Readable/Writeable; -n= value after reset, -x = undefined value after reset

Figure 9. GPIO Enable Register (GPEN) [Hex Address: 01B0 0000]

Figure 10 shows the GPIO direction bits in the GPDIR register. This register determines if a given GPIO pin is an input or an output providing the corresponding GPxEN bit is enabled (set to “1”) in the GPEN register. By default, all the GPIO pins are configured as input pins.

31

 

 

 

 

 

 

24

23

 

 

 

 

 

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R-0

 

 

 

 

 

 

 

 

15

14

13

12

 

10

9

8

 

6

5

4

 

3

2

1

0

11

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GP7

GP6

GP5

GP4

 

 

GP2

 

 

 

 

 

Reserved

 

 

 

DIR

DIR

DIR

DIR

 

—

DIR

—

—

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

 

R/W-0

R/W-0

R/W-0

R/W-0

Legend: R/W = Readable/Writeable; -n= value after reset, -x = undefined value after reset

Figure 10. GPIO Direction Register (GPDIR) [Hex Address: 01B0 0004]

For more detailed information on general-purpose inputs/outputs (GPIOs), see the TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRU584).

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Contents SPRS293A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing Bottom View GDP and ZDP BGA package bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA Package Description Characteristics of the C6712D Processor Device characteristicsHardware Features Internal Clock C6712DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1DA2 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryMemory Map Summary Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersMcBSP0 and McBSP1 Registers HEX Address Range Acronym Register Name Comments TimerClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst Signal groups descriptionJtag BIG/LITTLE EndianCLKR1 TOUT1 TINP1CLKS1† GpioDevice configurations at device reset Device ConfigurationsBOOTMODE10 Configuration GDP/ZDP Functional Description PINEmifbe LendianBIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions BOOTMODE1 C19 BOOTMODE0 C20 IPD BootmodeEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatOnly one asserted during any external data access IPD Description Name GDP IPU‡ ZDP Resets and InterruptsEdge-driven Decoded from the two lowest bits of the internal addressEmif − Data # Emif − Address #TIMER0 TIMER1IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Multichannel Buffered Serial Port 0 McBSP0GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV IPU IPD Description Name GDP IPU ZDPRSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November See the power-supply decoupling portion of this data sheet Name GDP ZDP Supply Voltage PinsDvdd CvddGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS GND Signal Name PIN GDP ZDP TYPE†VSS Description GDP Name ZDP Ground PinsHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Prefix Temperature Range Default 0C to 90CDevice Family TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitGDP 150and ZDP Clock SignalPLL Clock Frequency Ranges†‡ PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingPower-supply design considerations System-level design considerationsSupply Schottky Diode Core Supply Power-supply decouplingGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedBootmode Emif big endian mode correctnessReset Emif Data Lines Pins Where Data PresentIOH Recommended operating conditionsMIN NOM MAX Unit IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levels42 Ω Vref = 1.5= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure Input and Output ClocksTiming requirements for CLKIN†‡§ Clkin CLKOUT3 Timing requirements for ECLKIN§ see FigureEclkin Eclkout MINTiming requirements for asynchronous memory cycles†‡ Asynchronous Memory TimingSee −Figure AreCE30 BE10 EA212 Setup = Strobe = Not Ready Hold =ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy CEx BE30 EA212ED310 Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CE30 BE10EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†150 Synchronous Dram TimingTiming requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED150 EA2113 Write EclkoutEA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCE30 BE10 EA2113 Deac EclkoutEA112 EA12 ED150 Refr EclkoutCE30 BE10 EA212 MRS value ED150 MRS EclkoutTiming requirements for the HOLD/HOLDA cycles† see Figure HOLD/HOLDA TimingHold Hold HoldaEclkout Busreq Busreq TimingCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group † Emif Low Group † Boot and Device PhaseEXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Timing requirements for McBSP†‡ see Figure Multichannel Buffered Serial Port TimingParameter FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXBit Bitn-1 Parameter MASTER§ Slave Unit MIN MAXClkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Unit MIN MAX TCK TDO TDI/TMS/TRST Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure Thermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
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