Texas Instruments TMS320C6712D warranty DxEN

Page 51

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

PLL and PLL controller (continued)

PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers

(0x01B7 C114, 0x01B7 C118, 0x01B7 C11C, and 0x01B7 C120, respectively)

31

 

28

27

24

23

 

20

19

 

 

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R−0

 

 

 

 

 

 

15

14

12

 

8

 

5

4

 

2

1

0

11

7

3

 

 

 

 

 

 

 

 

 

 

 

 

DxEN

 

 

 

Reserved

 

 

 

 

PLLDIVx

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W−1

 

 

 

R−0

 

 

 

 

R/W−x xxxx †

 

 

Legend: R = Read only, R/W = Read/Write; -n = value after reset

†Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1 (0 0000), /1 (0 0000), /2 (0 0001), and /2 (0 0001), respectively.

CAUTION:

D1 and D2 should never be disabled. D3 should only be disabled if ECLKIN is used.

Table 30. PLL Wrapper Divider x Registers (Prescaler Divider D0 and Post-Scaler Dividers D1,

D2, and D3)‡

BIT #

NAME

 

 

DESCRIPTION

31:16

Reserved

Reserved. Read-only, writes have no effect.

 

 

 

 

 

Divider Dx Enable (where x denotes 0 through 3).

 

 

0

–

Divider x Disabled. No clock output.

15

DxEN

1

–

Divider x Enabled (default).

 

 

These divider-enable bits are device-specific and must be set to 1 to enable.

14:5

Reserved

Reserved. Read-only, writes have no effect.

 

 

 

 

 

PLL Divider Ratio [Default values for the PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 bits are /1, /1,

 

 

/2, and /2, respectively].

 

 

 

 

 

00000

=

/1

10000

=

/17

 

 

00001

=

/2

10001

=

/18

 

 

00010

=

/3

10010

=

/19

 

 

00011

=

/4

10011

=

/20

 

 

00100

=

/5

10100

=

/21

 

 

00101

=

/6

10101

=

/22

4:0

PLLDIVx

00110

=

/7

10110

=

/23

00111

=

/8

10111

=

/24

 

 

 

 

01000

=

/9

11000

=

/25

 

 

01001

=

/10

11001

=

/26

 

 

01010

=

/11

11010

=

/27

 

 

01011

=

/12

11011

=

/28

 

 

01100

=

/13

11100

=

/29

 

 

01101

=

/14

11101

=

/30

 

 

01110

=

/15

11110

=

/31

 

 

01111

=

/16

11111

=

/32

‡Note that SYSCLK2 must run at half the rate of SYSCLK1. Therefore, the divider ratio of D2 must be two times slower than D1. For example, if D1 is set to /2, then D2 must be set to /4.

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Contents SPRS293A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP BGA package bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PackageBottom View Description C6712D Device characteristicsCharacteristics of the C6712D Processor Hardware Features Internal ClockDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description ST2 ST1DA1 DA2Memory map summary Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache RegistersHEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM†Quick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersMcBSP0 and McBSP1 Registers HEX Address Range Acronym Register Name Comments TimerBIG/LITTLE Endian Signal groups descriptionClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst JtagGpio TOUT1 TINP1CLKR1 CLKS1†Device configurations at device reset Device ConfigurationsLendian Configuration GDP/ZDP Functional Description PINBOOTMODE10 EmifbeDevcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP LITTLE/BIG Endian Format BootmodeBOOTMODE1 C19 BOOTMODE0 C20 IPD EMU1B9 EMU0D9 IPUDecoded from the two lowest bits of the internal address IPD Description Name GDP IPU‡ ZDP Resets and InterruptsOnly one asserted during any external data access Edge-drivenEmif − Data # Emif − Address #Multichannel Buffered Serial Port 1 McBSP1 TIMER1TIMER0 IPD Description Name GDP IPU‡ ZDP Emif − Data #Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleReserved for Test Additional Reserved for Test IPD Description Name GDP IPU ZDPRSV IPU RSV IPDSPRS293A − October 2005 − Revised November Cvdd Name GDP ZDP Supply Voltage PinsSee the power-supply decoupling portion of this data sheet DvddGND Description Name GDP ZDP Supply Voltage PinsGround Pins VSSVSS GND Signal Name PIN GDP ZDP TYPE†VSS Description GDP Name ZDP Ground PinsDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Technology Temperature Range Default 0C to 90CPrefix Device FamilyDocumentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID PwrdCPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt SelectorEdma module and Edma selector Edma ChannelsEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or DisabledClock Signal PLL Clock Frequency Ranges†‡GDP 150and ZDP PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterSystem-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes Power-supply design considerationsC6000 Power-supply decouplingSupply Schottky Diode Core Supply GND DvddIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessBootmode ResetRecommended operating conditions MIN NOM MAX UnitIOH IOZ Parameter Test Conditions MIN TYP MAX UnitVref = 1.5 Signal transition levelsParameter Measurement Information 42 Ω= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Input and Output Clocks Timing requirements for CLKIN†‡§See Figure Clkin CLKOUT3 Timing requirements for ECLKIN§ see FigureEclkin Eclkout MINAre Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡ See −FigureAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Ardy Setup = Strobe = Not Ready Hold =CE30 BE10 EA212 ED150 Read DataCEx BE30 EA212 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE† CE30 BE10BE1 BE2 BE3 BE4 EA212 ED150Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure150 Read Eclkout EA2113 Bank EA112 Column EA12 ED150AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED150Dcab Eclkout Actv EclkoutCE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE†Refr Eclkout Deac EclkoutCE30 BE10 EA2113 EA112 EA12 ED150CE30 BE10 EA212 MRS value ED150 MRS EclkoutHold Holda HOLD/HOLDA TimingTiming requirements for the HOLD/HOLDA cycles† see Figure HoldEclkout Busreq Busreq TimingReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Emif Z Group † Emif Low Group † Boot and Device PhaseExternal Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Timing requirements for McBSP†‡ see Figure Multichannel Buffered Serial Port TimingParameter Clkx Clks ClkrFSR int Bitn-1Master Slave Unit MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resyncParameter MASTER§ Slave Unit MIN MAX Clkx FSXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Jtag TEST-PORT Timing Timing requirements for Jtag test port see FigureUnit MIN MAX TCK TDO TDI/TMS/TRST Mechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDPQty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak TempSeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
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