Texas Instruments TMS320C6712D warranty Peripheral register descriptions, Emif Registers

Page 13

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

peripheral register descriptions

Table 3 through Table 13 identify the peripheral registers for the device by their register names, acronyms, and hex address or hex address range. For more detailed information on the register contents, bit names, and their descriptions, see the specific peripheral reference guide listed in the TMS320C6000 DSP Peripherals Overview Reference Guide (literature number SPRU190).

 

 

Table 3. EMIF Registers

 

 

 

 

 

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

 

 

 

 

 

0180 0000

GBLCTL

EMIF global control

 

 

 

 

 

0180 0004

CECTL1

EMIF CE1 space control

 

 

 

 

 

0180 0008

CECTL0

EMIF CE0 space control

 

 

 

 

 

0180 000C

−

Reserved

 

 

 

 

 

0180 0010

CECTL2

EMIF CE2 space control

 

 

 

 

 

0180 0014

CECTL3

EMIF CE3 space control

 

 

 

 

 

0180 0018

SDCTL

EMIF SDRAM control

 

 

 

 

 

0180 001C

SDTIM

EMIF SDRAM refresh control

 

 

 

 

 

0180 0020

SDEXT

EMIF SDRAM extension

 

 

 

 

 

0180 0024 − 0183 FFFF

−

Reserved

 

 

 

Table 4. L2 Cache Registers

 

 

 

 

 

HEX ADDRESS RANGE

ACRONYM

REGISTER NAME

 

 

 

 

 

0184 0000

CCFG

Cache configuration register

 

 

 

 

 

0184 4000

L2WBAR

L2 writeback base address register

 

 

 

 

 

0184 4004

L2WWC

L2 writeback word count register

 

 

 

 

 

0184 4010

L2WIBAR

L2 writeback-invalidate base address register

 

 

 

 

 

0184 4014

L2WIWC

L2 writeback-invalidate word count register

 

 

 

 

 

0184 4020

L1PIBAR

L1P invalidate base address register

 

 

 

 

 

0184 4024

L1PIWC

L1P invalidate word count register

 

 

 

 

 

0184 4030

L1DWIBAR

L1D writeback-invalidate base address register

 

 

 

 

 

0184 4034

L1DWIWC

L1D writeback-invalidate word count register

 

 

 

 

 

0184 5000

L2WB

L2 writeback all register

 

 

 

 

 

0184 5004

L2WBINV

L2 writeback-invalidate all register

 

 

 

 

 

0184 8200

MAR0

Controls CE0 range 8000 0000 − 80FF FFFF

 

 

 

 

 

0184 8204

MAR1

Controls CE0 range 8100 0000 − 81FF FFFF

 

 

 

 

 

0184 8208

MAR2

Controls CE0 range 8200 0000 − 82FF FFFF

 

 

 

 

 

0184 820C

MAR3

Controls CE0 range 8300 0000 − 83FF FFFF

 

 

 

 

 

0184 8240

MAR4

Controls CE1 range 9000 0000 − 90FF FFFF

 

 

 

 

 

0184 8244

MAR5

Controls CE1 range 9100 0000 − 91FF FFFF

 

 

 

 

 

0184 8248

MAR6

Controls CE1 range 9200 0000 − 92FF FFFF

 

 

 

 

 

0184 824C

MAR7

Controls CE1 range 9300 0000 − 93FF FFFF

 

 

 

 

 

0184 8280

MAR8

Controls CE2 range A000 0000 − A0FF FFFF

 

 

 

 

 

0184 8284

MAR9

Controls CE2 range A100 0000 − A1FF FFFF

 

 

 

 

 

0184 8288

MAR10

Controls CE2 range A200 0000 − A2FF FFFF

 

 

 

 

 

0184 828C

MAR11

Controls CE2 range A300 0000 − A3FF FFFF

 

 

 

 

 

0184 82C0

MAR12

Controls CE3 range B000 0000 − B0FF FFFF

 

 

 

 

 

0184 82C4

MAR13

Controls CE3 range B100 0000 − B1FF FFFF

 

 

 

 

 

0184 82C8

MAR14

Controls CE3 range B200 0000 − B2FF FFFF

 

 

 

 

 

0184 82CC

MAR15

Controls CE3 range B300 0000 − B3FF FFFF

 

 

 

 

 

0184 82D0 − 0187 FFFF

−

Reserved

 

 

 

 

 

 

 

 

 

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

13

Page 12 Page 14
Image 13
Page 12 Page 14
Contents SPRS293A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA Package GDP and ZDP BGA package bottom viewBottom View Description Characteristics of the C6712D Processor Device characteristicsHardware Features Internal Clock C6712DDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description DA1 ST1DA2 ST2Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register NameDevice Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsQuick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersMcBSP0 and McBSP1 Registers HEX Address Range Acronym Register Name Comments TimerClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst Signal groups descriptionJtag BIG/LITTLE EndianCLKR1 TOUT1 TINP1CLKS1† GpioDevice configurations at device reset Device ConfigurationsBOOTMODE10 Configuration GDP/ZDP Functional Description PINEmifbe LendianEksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP BOOTMODE1 C19 BOOTMODE0 C20 IPD BootmodeEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatOnly one asserted during any external data access IPD Description Name GDP IPU‡ ZDP Resets and InterruptsEdge-driven Decoded from the two lowest bits of the internal addressEmif − Data # Emif − Address #TIMER0 TIMER1IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0Reserved for Test RSV IPU IPD Description Name GDP IPU ZDPRSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November See the power-supply decoupling portion of this data sheet Name GDP ZDP Supply Voltage PinsDvdd CvddGround Pins Description Name GDP ZDP Supply Voltage PinsVSS GNDVSS GND Signal Name PIN GDP ZDP TYPE†VSS Description GDP Name ZDP Ground PinsSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Prefix Temperature Range Default 0C to 90CDevice Family TechnologyDocumentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIECPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector EventEdma Channels Edma module and Edma selectorEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX UnitPLL Clock Frequency Ranges†‡ Clock SignalGDP 150and ZDP PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterCharacteristics of the Power-Down Modes Power-supply sequencingPower-supply design considerations System-level design considerationsSupply Schottky Diode Core Supply Power-supply decouplingGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedBootmode Emif big endian mode correctnessReset Emif Data Lines Pins Where Data PresentMIN NOM MAX Unit Recommended operating conditionsIOH IOZ Parameter Test Conditions MIN TYP MAX UnitParameter Measurement Information Signal transition levels42 Ω Vref = 1.5= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Timing requirements for CLKIN†‡§ Input and Output ClocksSee Figure Clkin CLKOUT3 Timing requirements for ECLKIN§ see FigureEclkin Eclkout MINTiming requirements for asynchronous memory cycles†‡ Asynchronous Memory TimingSee −Figure AreCE30 BE10 EA212 Setup = Strobe = Not Ready Hold =ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyED310 CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Unit MIN MAX SYNCHRONOUS-BURST Memory TimingBE1 BE2 BE3 BE4 CE30 BE10EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing150 EA2113 Bank EA112 Column EA12 ED150 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA2113 Write EclkoutEA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutCE30 BE10 EA2113 Deac EclkoutEA112 EA12 ED150 Refr EclkoutCE30 BE10 EA212 MRS value ED150 MRS EclkoutTiming requirements for the HOLD/HOLDA cycles† see Figure HOLD/HOLDA TimingHold Hold HoldaEclkout Busreq Busreq TimingTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Emif Z Group † Emif Low Group † Boot and Device PhaseTiming requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Timing requirements for McBSP†‡ see Figure Multichannel Buffered Serial Port TimingParameter FSR int Clks ClkrBitn-1 ClkxClks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXClkx FSX Parameter MASTER§ Slave Unit MIN MAXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Timing requirements for Jtag test port see Figure Jtag TEST-PORT TimingUnit MIN MAX TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical DataPackaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp QtySeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
Top Page Image Contents