Texas Instruments TMS320C6712D warranty CPU DSP core description

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

CPU (DSP core) description

The CPU fetches advanced very-long instruction words (VLIW) (256 bits wide) to supply up to eight 32-bit instructions to the eight functional units during every clock cycle. The VLIW architecture features controls by which all eight units do not have to be supplied with instructions if they are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs to the same execute packet as the previous instruction, or whether it should be executed in the following clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute packets can vary in size. The variable-length execute packets are a key memory-saving feature, distinguishing the C67x CPU from other VLIW architectures.

The CPU features two sets of functional units. Each set contains four units and a register file. One set contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The two register files each contain 16 32-bit registers for a total of 32 general-purpose registers. The two sets of functional units, along with two register files, compose sides A and B of the CPU [see the functional block and CPU (DSP Core) diagram and Figure 1]. The four functional units on each side of the CPU can freely share the 16 registers belonging to that side. Additionally, each side features a single data bus connected to all the registers on the other side, by which the two sets of functional units can access data from the register files on the opposite side. While register access by functional units on the same side of the CPU as the register file can service all the units in a single clock cycle, register access using the register file across the CPU supports one read and one write per cycle.

The C67x CPU executes all C62xDSP instructions. In addition to C62xfixed-point DSP instructions, the six out of eight functional units (.L1, .M1, .D1, .D2, .M2, and .L2) also execute floating-point instructions. The remaining two functional units (.S1 and .S2) also execute the new LDDW instruction which loads 64 bits per CPU side for a total of 128 bits per cycle.

Another key feature of the C67x CPU is the load/store architecture, where all instructions operate on registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are responsible for all data transfers between the register files and the memory. The data address driven by the .D units allows data addresses generated from one register file to be used to load or store data to or from the other register file. The C67x CPU supports a variety of indirect addressing modes using either linear- or circular-addressing modes with 5- or 15-bit offsets. All instructions are conditional, and most can access any one of the 32 registers. Some registers, however, are singled out to support specific addressing or to hold the condition for conditional instructions (if the condition is not automatically “true”). The two .M functional units are dedicated for multiplies. The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with results available every clock cycle.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program memory. The 32-bit instructions destined for the individual functional units are “linked” together by “1” bits in the least significant bit (LSB) position of the instructions. The instructions that are “chained” together for simultaneous execution (up to eight in total) compose an execute packet. A “0” in the LSB of an instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. If an execute packet crosses the fetch-packet boundary (256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch packet is padded with NOP instructions. The number of execute packets within a fetch packet can vary from one to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch packet have been dispatched. After decoding, the instructions simultaneously drive all active functional units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in 32-bit registers, they can be subsequently moved to memory as bytes or half-words as well. All load and store instructions are byte-, half-word, or word-addressable.

C62x is a trademark of Texas Instruments.

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Contents SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA Package GDP and ZDP BGA package bottom viewBottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6712D Processor C6712DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description DA2 ST1DA1 ST2Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register NameEdma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersJtag Signal groups descriptionClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst BIG/LITTLE EndianCLKS1† TOUT1 TINP1CLKR1 GpioDevice Configurations Device configurations at device resetEmifbe Configuration GDP/ZDP Functional Description PINBOOTMODE10 LendianEksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP EMU1B9 EMU0D9 IPU BootmodeBOOTMODE1 C19 BOOTMODE0 C20 IPD LITTLE/BIG Endian FormatEdge-driven IPD Description Name GDP IPU‡ ZDP Resets and InterruptsOnly one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − Address # Emif − Data #IPD Description Name GDP IPU‡ ZDP Emif − Data # TIMER1TIMER0 Multichannel Buffered Serial Port 1 McBSP1GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0Reserved for Test RSV IPD IPD Description Name GDP IPU ZDPRSV IPU Additional Reserved for TestSPRS293A − October 2005 − Revised November Dvdd Name GDP ZDP Supply Voltage PinsSee the power-supply decoupling portion of this data sheet CvddVSS Description Name GDP ZDP Supply Voltage PinsGround Pins GNDSignal Name PIN GDP ZDP TYPE† VSS GNDDescription GDP Name ZDP Ground Pins VSSSoftware Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Device Family Temperature Range Default 0C to 90CPrefix TechnologyDocumentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIECPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector EventEdma Channels Edma module and Edma selectorEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX UnitPLL Clock Frequency Ranges†‡ Clock SignalGDP 150and ZDP Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply design considerations Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsGND Dvdd Power-supply decouplingSupply Schottky Diode Core Supply C6000Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedReset Emif big endian mode correctnessBootmode Emif Data Lines Pins Where Data PresentMIN NOM MAX Unit Recommended operating conditionsIOH Parameter Test Conditions MIN TYP MAX Unit IOZ42 Ω Signal transition levelsParameter Measurement Information Vref = 1.5AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Timing requirements for CLKIN†‡§ Input and Output ClocksSee Figure Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3MIN Eclkin EclkoutSee −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡ AreED150 Read Data Setup = Strobe = Not Ready Hold =CE30 BE10 EA212 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyED310 CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXEA212 ED150 CE30 BE10BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing150 EA2113 Bank EA112 Column EA12 ED150 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED150 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Dcab EclkoutEA112 EA12 ED150 Deac EclkoutCE30 BE10 EA2113 Refr EclkoutMRS Eclkout CE30 BE10 EA212 MRS value ED150Hold HOLD/HOLDA TimingTiming requirements for the HOLD/HOLDA cycles† see Figure Hold HoldaBusreq Timing Eclkout BusreqTiming requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Phase Emif Z Group † Emif Low Group † Boot and DeviceTiming requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see FigureParameter Bitn-1 Clks ClkrFSR int ClkxFSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave Unit MIN MAXClkx FSX Parameter MASTER§ Slave Unit MIN MAXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Timing requirements for Jtag test port see Figure Jtag TEST-PORT TimingUnit MIN MAX TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical DataMSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
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