Texas Instruments TMS320C6712D warranty PLL Clock Frequency Ranges†‡, Clock Signal, GDP 150and ZDP

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

PLL and PLL controller (continued)

Table 27. PLL Clock Frequency Ranges†‡

CLOCK SIGNAL

 

GDP 150and ZDP 150

UNIT

 

 

 

MIN

 

MAX

 

 

 

 

 

 

 

 

PLLREF (PLLEN = 1)

12

 

100

MHz

 

 

 

 

 

PLLOUT

140

 

600

MHz

 

 

 

 

 

SYSCLK1

−

 

Device Speed (DSP Core)

MHz

 

 

 

 

 

SYSCLK3 (EKSRC = 0)

−

 

100

MHz

 

 

 

 

 

†SYSCLK2 rate must be exactly half of SYSCLK1.

‡Also see the electrical specification (timing requirements and switching characteristics parameters) in the Input and Output Clocks section of this data sheet.

The EMIF itself may be clocked by an external reference clock via the ECLKIN pin or can be generated on-chip as SYSCLK3. SYSCLK3 is derived from divider D3 off of PLLOUT (see Figure 8, PLL and Clock Generator Logic). The EMIF clock selection is programmable via the EKSRC bit in the DEVCFG register.

The settings for the PLL multiplier and each of the dividers in the clock generation block may be reconfigured via software at run time. If either the input to the PLL changes due to D0, CLKMODE0, or CLKIN, or if the PLL multiplier is changed, then software must enter bypass first and stay in bypass until the PLL has had enough time to lock (see electrical specifications). For the programming procedure, see the TMS320C6000 DSP Software-ProgrammablePhase-Locked Loop (PLL) Controller Reference Guide (literature number SPRU233).

SYSCLK2 is the internal clock source for peripheral bus control. SYSCLK2 (Divider D2) must be programmed to be half of the SYSCLK1 rate. For example, if D1 is configured to divide-by-2 mode (/2), then D2 must be programmed to divide-by-4 mode (/4). SYSCLK2 is also tied directly to CLKOUT2 pin (see Figure 8).

During the programming transition of Divider D1 and Divider D2 (resulting in SYSCLK1 and SYSCLK2 output clocks, see Figure 8), the order of programming the PLLDIV1 and PLLDIV2 registers must be observed to ensure that SYSCLK2 always runs at half the SYSCLK1 rate or slower. For example, if the divider ratios of D1 and D2 are to be changed from /1, /2 (respectively) to /5, /10 (respectively) then, the PLLDIV2 register must be programmed before the PLLDIV1 register. The transition ratios become /1, /2; /1, /10; and then /5, /10. If the divider ratios of D1 and D2 are to be changed from /3, /6 to /1, /2 then, the PLLDIV1 register must be programmed before the PLLDIV2 register. The transition ratios, for this case, become /3, /6; /1, /6; and then /1, /2. The final SYSCLK2 rate must be exactly half of the SYSCLK1 rate.

Note that Divider D1 and Divider D2 must always be enabled (i.e., D1EN and D2EN bits are set to “1” in the PLLDIV1 and PLLDIV2 registers).

For detailed information on the clock generator (PLL Controller registers) and their associated software bit descriptions, see Table 28 through Table 31.

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Contents SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA package bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PackageBottom View Description Device characteristics Characteristics of the C6712D ProcessorHardware Features Internal Clock C6712DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description ST1 DA1DA2 ST2Memory map summary Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register NameInterrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersSignal groups description Clkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK TrstJtag BIG/LITTLE EndianTOUT1 TINP1 CLKR1CLKS1† GpioDevice Configurations Device configurations at device resetConfiguration GDP/ZDP Functional Description PIN BOOTMODE10Emifbe LendianDevcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP Bootmode BOOTMODE1 C19 BOOTMODE0 C20 IPDEMU1B9 EMU0D9 IPU LITTLE/BIG Endian FormatIPD Description Name GDP IPU‡ ZDP Resets and Interrupts Only one asserted during any external data accessEdge-driven Decoded from the two lowest bits of the internal addressEmif − Address # Emif − Data #TIMER1 TIMER0IPD Description Name GDP IPU‡ ZDP Emif − Data # Multichannel Buffered Serial Port 1 McBSP1Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio ModuleReserved for Test IPD Description Name GDP IPU ZDP RSV IPURSV IPD Additional Reserved for TestSPRS293A − October 2005 − Revised November Name GDP ZDP Supply Voltage Pins See the power-supply decoupling portion of this data sheetDvdd CvddDescription Name GDP ZDP Supply Voltage Pins Ground PinsVSS GNDSignal Name PIN GDP ZDP TYPE† VSS GNDDescription GDP Name ZDP Ground Pins VSSDevelopment support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Temperature Range Default 0C to 90C PrefixDevice Family TechnologyDocumentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIECPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector EventEdma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX UnitClock Signal PLL Clock Frequency Ranges†‡GDP 150and ZDP Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply sequencing Characteristics of the Power-Down ModesPower-supply design considerations System-level design considerationsPower-supply decoupling Supply Schottky Diode Core SupplyGND Dvdd C6000Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedEmif big endian mode correctness BootmodeReset Emif Data Lines Pins Where Data PresentRecommended operating conditions MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZSignal transition levels Parameter Measurement Information42 Ω Vref = 1.5AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Input and Output Clocks Timing requirements for CLKIN†‡§See Figure Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3MIN Eclkin EclkoutAsynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡See −Figure AreSetup = Strobe = Not Ready Hold = CE30 BE10 EA212ED150 Read Data AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyCEx BE30 EA212 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Unit MIN MAXCE30 BE10 BE1 BE2 BE3 BE4EA212 ED150 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure150 Read Eclkout EA2113 Bank EA112 Column EA12 ED150AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †Actv Eclkout CE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab EclkoutDeac Eclkout CE30 BE10 EA2113EA112 EA12 ED150 Refr EclkoutMRS Eclkout CE30 BE10 EA212 MRS value ED150HOLD/HOLDA Timing Timing requirements for the HOLD/HOLDA cycles† see FigureHold Hold HoldaBusreq Timing Eclkout BusreqReset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Emif Z Group † Emif Low Group † Boot and DeviceExternal Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see FigureParameter Clks Clkr FSR intBitn-1 ClkxTiming requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave Unit MIN MAXParameter MASTER§ Slave Unit MIN MAX Clkx FSXBit Bitn-1 McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Jtag TEST-PORT Timing Timing requirements for Jtag test port see FigureUnit MIN MAX TCK TDO TDI/TMS/TRST Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical DataOrderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
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