Texas Instruments TMS320C6712D warranty Parameter Test Conditions MIN TYP MAX Unit, Ioz

Page 62

SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

electrical characteristics over recommended ranges of supply voltage and operating case temperature† (unless otherwise noted)

 

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

 

 

 

 

 

 

 

 

VOH

High-level output

All signals except CLKS1 and

DVDD = MIN, IOH = MAX

2.4

 

 

V

voltage

DR1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Low-level output

All signals except CLKS1 and

 

 

 

0.4

V

VOL

DR1

DVDD = MIN, IOL = MAX

 

 

voltage

 

 

 

 

 

 

 

 

 

 

CLKS1 and DR1

 

 

 

0.4

V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All signals except CLKS1 and

 

 

 

±170

uA

II

Input current

DR1

VI = VSS to DVDD

 

 

 

 

 

 

 

 

CLKS1 and DR1

 

 

 

±10

uA

 

 

 

 

 

 

 

 

 

Off-state output

All signals except CLKS1 and

 

 

 

±170

uA

IOZ

DR1

VO = DVDD or 0 V

 

 

current

 

 

 

 

 

CLKS1 and DR1

 

 

 

±10

uA

 

 

 

 

 

 

 

 

 

 

 

 

 

I

Core supply current‡

 

CVDD = 1.26 V, CPU

 

430

 

mA

DD2V

 

 

clock = 150 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDD3V

I/O supply current‡

 

DVDD = 3.3 V,

 

75

 

mA

 

EMIF speed = 100 MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ci

Input capacitance

C6712D

 

 

 

7

pF

Co

Output capacitance

C6712D

 

 

 

7

pF

†For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.

‡For more details on CPU, peripheral, and I/O activity, see the TMS320C62x/C67x Power Consumption Summary application report (literature

number SPRA486).

For the device, these currents were measured with average activity (50% high/50% low power) at 25°C case temperature and 100-MHz EMIF. This model represents a device performing high-DSP-activity operations 50% of the time, and the remainder performing low-DSP-activity operations. The high/low-DSP-activity models are defined as follows:

High-DSP-Activity Model:

CPU: 8 instructions/cycle with 2 LDDW instructions [L1 Data Memory: 128 bits/cycle via LDDW instructions;

L1 Program Memory: 256 bits/cycle; L2/EMIF EDMA: 50% writes, 50% reads to/from SDRAM (50% bit-switching)] McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate Low-DSP-Activity Model:

CPU: 2 instructions/cycle with 1 LDH instruction [L1 Data Memory: 16 bits/cycle; L1 Program Memory: 256 bits per 4 cycles; L2/EMIF EDMA: None]

McBSP: 2 channels at E1 rate

Timers: 2 timers at maximum rate

The actual current draw is highly application-dependent. For more details on core and I/O activity, refer to the TMS320C6711D/12D/13B Power Consumption Summary application report (literature number SPRA889A).

62

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Page 61 Page 63
Image 62
Page 61 Page 63
Contents SPRS293A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing Bottom View GDP and ZDP BGA package bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA Package Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6712D Processor C6712DDevice compatibility Functional block and CPU DSP core diagram Digital Signal ProcessorCPU DSP core description DA2 ST1DA1 ST2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryMemory Map Summary L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register NameEdma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name CommentsEdma Registers Quick DMA Qdma and Pseudo Registers†PLL Controller Registers Gpio RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 RegistersJtag Signal groups descriptionClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst BIG/LITTLE EndianCLKS1† TOUT1 TINP1CLKR1 GpioDevice Configurations Device configurations at device resetEmifbe Configuration GDP/ZDP Functional Description PINBOOTMODE10 LendianBIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions EMU1B9 EMU0D9 IPU BootmodeBOOTMODE1 C19 BOOTMODE0 C20 IPD LITTLE/BIG Endian FormatEdge-driven IPD Description Name GDP IPU‡ ZDP Resets and InterruptsOnly one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − Address # Emif − Data #IPD Description Name GDP IPU‡ ZDP Emif − Data # TIMER1TIMER0 Multichannel Buffered Serial Port 1 McBSP1Reserved for Test Multichannel Buffered Serial Port 0 McBSP0GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV IPD IPD Description Name GDP IPU ZDPRSV IPU Additional Reserved for TestSPRS293A − October 2005 − Revised November Dvdd Name GDP ZDP Supply Voltage PinsSee the power-supply decoupling portion of this data sheet CvddVSS Description Name GDP ZDP Supply Voltage PinsGround Pins GNDSignal Name PIN GDP ZDP TYPE† VSS GNDDescription GDP Name ZDP Ground Pins VSSHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Device Family Temperature Range Default 0C to 90CPrefix TechnologyDocumentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIEPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector EventEdma Selector Edma module and Edma selectorEdma Channels ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0CPLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX UnitGDP 150and ZDP Clock SignalPLL Clock Frequency Ranges†‡ Pllcsr Register 0x01B7 C100 PLL Control/Status Register PllcsrPllm Register 0x01B7 C110 PLL Multiplier Control Register PllmDxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1Power-supply design considerations Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerationsGND Dvdd Power-supply decouplingSupply Schottky Diode Core Supply C6000Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif SpeedReset Emif big endian mode correctnessBootmode Emif Data Lines Pins Where Data PresentIOH Recommended operating conditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit IOZ42 Ω Signal transition levelsParameter Measurement Information Vref = 1.5AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max GroundTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure Input and Output ClocksTiming requirements for CLKIN†‡§ Timing requirements for ECLKIN§ see Figure Clkin CLKOUT3MIN Eclkin EclkoutSee −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡ AreED150 Read Data Setup = Strobe = Not Ready Hold =CE30 BE10 EA212 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† ArdyAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy CEx BE30 EA212ED310 SYNCHRONOUS-BURST Memory Timing Unit MIN MAXEA212 ED150 CE30 BE10BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE†150 Synchronous Dram TimingTiming requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED150 EA12 ED150 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE †AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 Dcab EclkoutEA112 EA12 ED150 Deac EclkoutCE30 BE10 EA2113 Refr EclkoutMRS Eclkout CE30 BE10 EA212 MRS value ED150Hold HOLD/HOLDA TimingTiming requirements for the HOLD/HOLDA cycles† see Figure Hold HoldaBusreq Timing Eclkout BusreqCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Phase Emif Z Group † Emif Low Group † Boot and DeviceEXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Multichannel Buffered Serial Port Timing Timing requirements for McBSP†‡ see FigureParameter Bitn-1 Clks ClkrFSR int ClkxFSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave Unit MIN MAXBit Bitn-1 Parameter MASTER§ Slave Unit MIN MAXClkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Unit MIN MAX TCK TDO TDI/TMS/TRST Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure Thermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical DataMSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information QtyGDP S-PBGA-N272 Seating Plane 4204396/A 04/02ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
Top Page Image Contents