Texas Instruments TMS320C6712D PLL Lock and Reset Times, MIN TYP MAX Unit, Enabled or Disabled

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SPRS293A − OCTOBER 2005 − REVISED NOVEMBER 2005

PLL and PLL controller (continued)

The PLL Reset Time is the amount of wait time needed when resetting the PLL (writing PLLRST=1), in order for the PLL to properly reset, before bringing the PLL out of reset (writing PLLRST = 0). For the PLL Reset Time value, see Table 25. The PLL Lock Time is the amount of time from when PLLRST = 0 with PLLEN = 0 (PLL out of reset, but still bypassed) to when the PLLEN bit can be safely changed to “1” (switching from bypass to the PLL path), see Table 25 and Figure 8.

Under some operating conditions, the maximum PLL Lock Time may vary from the specified typical value. For the PLL Lock Time values, see Table 25.

Table 25. PLL Lock and Reset Times

 

MIN

TYP

MAX

UNIT

 

 

 

 

 

PLL Lock Time

 

75

187.5

∝s

 

 

 

 

 

PLL Reset Time

125

 

 

ns

Table 26 shows the device’s CLKOUT signals, how they are derived and by what register control bits, and the default settings. For more details on the PLL, see the PLL and Clock Generator Logic diagram (Figure 8).

Table 26. CLKOUT Signals, Default Settings, and Control

CLOCK OUTPUT

DEFAULT SETTING

CONTROL

DESCRIPTION

SIGNAL NAME

(ENABLED or DISABLED)

BIT(s) (Register)

 

 

 

 

 

CLKOUT2

ON (ENABLED)

D2EN = 1 (PLLDIV2.[15])

SYSCLK2 selected [default]

CK2EN = 1 (EMIF GBLCTL.[3])

 

 

 

 

 

 

 

CLKOUT3

ON (ENABLED)

OD1EN = 1 (OSCDIV1.[15])

Derived from CLKIN

 

 

 

 

 

 

 

SYSCLK3 selected [default].

ECLKOUT

ON (ENABLED);

EKSRC = 0 (DEVCFG.[4])

To select ECLKIN as source:

derived from SYSCLK3

EKEN = 1 (EMIF GBLCTL.[5])

 

EKSRC = 1 (DEVCFG.[4]) and

 

 

 

 

 

 

EKEN = 1 (EMIF GBLCTL.[5])

 

 

 

 

This input clock is directly available as an internal high-frequency clock source that may be divided down by a programmable divider OSCDIV1 (/1, /2, /3, ..., /32) and output on the CLKOUT3 pin for other use in the system.

Figure 8 shows that the input clock source may be divided down by divider PLLDIV0 (/1, /2, ..., /32) and then multiplied up by a factor of x4, x5, x6, and so on, up to x25.

Either the input clock (PLLEN = 0) or the PLL output (PLLEN = 1) then serves as the high-frequency reference clock for the rest of the DSP system. The DSP core clock, the peripheral bus clock, and the EMIF clock may be divided down from this high-frequency clock (each with a unique divider) . For example, with a 40-MHz input, if the PLL output is configured for 300 MHz, the DSP core may be operated at 150 MHz (/2) while the EMIF may be configured to operate at a rate of 60 MHz (/5). Note that there is a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the block labeled PLL in Figure 8, as well as for the DSP core, peripheral bus, and EMIF. The clock generator must not be configured to exceed any of these constraints (certain combinations of external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 27 for the PLL clocks input and output frequency ranges.

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Contents SPRS293A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing Bottom View GDP and ZDP BGA package bottom viewGDP and ZDP 272-PIN Ball Grid Array BGA Package Description C6712D Device characteristicsCharacteristics of the C6712D Processor Hardware Features Internal ClockDevice compatibility Digital Signal Processor Functional block and CPU DSP core diagramCPU DSP core description ST2 ST1DA1 DA2Memory Block Description Block Size Bytes HEX Address Range Memory map summaryMemory Map Summary HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache RegistersHEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM†Quick DMA Qdma and Pseudo Registers† Edma RegistersGpio Registers PLL Controller RegistersMcBSP0 and McBSP1 Registers HEX Address Range Acronym Register Name Comments TimerBIG/LITTLE Endian Signal groups descriptionClkin CLKOUT3 CLKOUT2† CLKMODE0 Pllhv TMS TDO TDI TCK Trst JtagGpio TOUT1 TINP1CLKR1 CLKS1†Device configurations at device reset Device ConfigurationsLendian Configuration GDP/ZDP Functional Description PINBOOTMODE10 EmifbeBIT # Name Description Devcfg register descriptionEksrc Terminal Functions IPD Description Name GDP IPU‡ ZDP PIN SignalTerminal Functions LITTLE/BIG Endian Format BootmodeBOOTMODE1 C19 BOOTMODE0 C20 IPD EMU1B9 EMU0D9 IPUDecoded from the two lowest bits of the internal address IPD Description Name GDP IPU‡ ZDP Resets and InterruptsOnly one asserted during any external data access Edge-drivenEmif − Data # Emif − Address #Multichannel Buffered Serial Port 1 McBSP1 TIMER1TIMER0 IPD Description Name GDP IPU‡ ZDP Emif − Data #Reserved for Test Multichannel Buffered Serial Port 0 McBSP0GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Additional Reserved for Test IPD Description Name GDP IPU ZDPRSV IPU RSV IPDSPRS293A − October 2005 − Revised November Cvdd Name GDP ZDP Supply Voltage PinsSee the power-supply decoupling portion of this data sheet DvddGND Description Name GDP ZDP Supply Voltage PinsGround Pins VSSVSS GND Signal Name PIN GDP ZDP TYPE†VSS Description GDP Name ZDP Ground PinsHardware Development Tools Development supportSoftware Development Tools Fully qualified production device Device supportDevice and development-support tool nomenclature Technology Temperature Range Default 0C to 90CPrefix Device FamilyDocumentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID PwrdPCC CPU CSR Register Bit Field DescriptionCPU ID L2MODE Cache configuration Ccfg register descriptionCcfg Register Bit Field Description Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt SelectorEdma Selector Edma module and Edma selectorEdma Channels ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or DisabledGDP 150and ZDP Clock SignalPLL Clock Frequency Ranges†‡ PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110DxEN OD1EN OSCDIV1 Register 0x01B7 C124Oscillator Divider 1 Register OSCDIV1 DIR General-purpose input/output GpioGP7 GP6 GP5 GP4 GP2 Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR RegisterSystem-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes Power-supply design considerationsC6000 Power-supply decouplingSupply Schottky Diode Core Supply GND DvddIeee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speedEmif Data Lines Pins Where Data Present Emif big endian mode correctnessBootmode ResetIOH Recommended operating conditionsMIN NOM MAX Unit IOZ Parameter Test Conditions MIN TYP MAX UnitVref = 1.5 Signal transition levelsParameter Measurement Information 42 Ω= 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specificationsTiming parameters and board routing analysis Output from DSP Control Signals † Output from DSPBoard-Level Timings Example see Figure See Figure Input and Output ClocksTiming requirements for CLKIN†‡§ Clkin CLKOUT3 Timing requirements for ECLKIN§ see FigureEclkin Eclkout MINAre Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡ See −FigureAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Ardy Setup = Strobe = Not Ready Hold =CE30 BE10 EA212 ED150 Read DataAOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy CEx BE30 EA212ED310 Unit MIN MAX SYNCHRONOUS-BURST Memory TimingARE/SDCAS/SSADS † AOE/SDRAS/SSOE † AWE/SDWE/SSWE† CE30 BE10BE1 BE2 BE3 BE4 EA212 ED150150 Synchronous Dram TimingTiming requirements for synchronous Dram cycles† see Figure AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Read EclkoutEA2113 Bank EA112 Column EA12 ED150 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED150Dcab Eclkout Actv EclkoutCE30 BE10 EA2113 Bank Activate EA112 Row Address EA12 ED150 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE†Refr Eclkout Deac EclkoutCE30 BE10 EA2113 EA112 EA12 ED150CE30 BE10 EA212 MRS value ED150 MRS EclkoutHold Holda HOLD/HOLDA TimingTiming requirements for the HOLD/HOLDA cycles† see Figure HoldEclkout Busreq Busreq TimingCLKMODE0 = Reset TimingTiming requirements for reset†‡ see Figure Emif Z Group † Emif Low Group † Boot and Device PhaseEXTINT, NMI External Interrupt TimingTiming requirements for external interrupts† see Figure Timing requirements for McBSP†‡ see Figure Multichannel Buffered Serial Port TimingParameter Clkx Clks ClkrFSR int Bitn-1Master Slave Unit MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resyncBit Bitn-1 Parameter MASTER§ Slave Unit MIN MAXClkx FSX McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Multichannel Buffered Serial Port Timing McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = TINPx TOUTx Timer TimingTiming requirements for timer inputs† GPIx GPOx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingTiming requirements for Gpio inputs†‡ Unit MIN MAX TCK TDO TDI/TMS/TRST Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure Mechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDPQty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak TempSeating Plane 4204396/A 04/02 GDP S-PBGA-N272Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272Important Notice

TMS320C6712D specifications

The Texas Instruments TMS320C6712D is a high-performance, fixed-point digital signal processor (DSP) that belongs to the TMS320C6000 family, well known for its advanced processing capabilities tailored for demanding signal processing applications. Launched in the early 2000s, the C6712D combines high computational power with a rich set of features, making it suitable for a variety of applications such as telecommunications, audio processing, and industrial control systems.

One of the standout characteristics of the TMS320C6712D is its architecture, which is based on a highly efficient VLIW (Very Long Instruction Word) design. This architecture allows the processor to execute multiple instructions in a single clock cycle, significantly increasing performance. The device operates at clock speeds of up to 150 MHz, providing substantial computational throughput that can handle complex algorithms and real-time processing tasks.

Another key feature of the TMS320C6712D is its 32-bit fixed-point processing capabilities, which allows it to perform difficult mathematical computations efficiently. With an instruction set optimized for DSP applications, the processor includes specialized instructions for multiplying and accumulating operations, as well as support for advanced filtering and generation of audio signals.

The C6712D offers an extensive memory architecture, supporting up to 128 MB of external memory via a 32-bit data bus. It features on-chip SRAM, which provides fast access to data and program storage, enhancing the system's overall performance. Additionally, the device includes a powerful set of peripherals, such as dual asynchronous serial ports (UART), I2C interfaces, and DSP-specific interfaces that facilitate connectivity with other components and systems.

Power consumption is another vital aspect of the TMS320C6712D. It incorporates technologies allowing for low-power operation, which is essential for portable and battery-operated devices. The capability to operate in various power modes helps optimize performance while minimizing energy usage.

In conclusion, the Texas Instruments TMS320C6712D is a versatile and powerful DSP that excels in high-performance applications. Its VLIW architecture, fixed-point processing capabilities, extensive memory options, and low power consumption make it an ideal choice for engineers looking to implement complex signal processing tasks efficiently. Whether used in telecommunications, audio processing, or industrial applications, the C6712D remains a reliable and capable solution in the digital signal processing landscape.
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