AMD manual AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet

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31994A —1August 2004

AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

clock must be valid at this time. The system clocks are designed to be running after 3.3 V has been within specification for three milliseconds.

4.PWROK assertion to deassertion of RESET#

The duration of RESET# assertion during cold boots is intended to satisfy the time it takes for the PLL to lock with a less than 1 ns phase error. The processor PLL begins to run after PWROK is asserted and the internal clock grid is switched from the ring oscillator to the PLL. The PLL lock time may take from hundreds of nanoseconds to tens of microseconds. It is recommended that the minimum time between PWROK assertion to the deassertion of RESET# be at least 1.0 milliseconds. Southbridges enforce a delay of 1.5 to 2.0 milliseconds between PWRGD (Southbridge version of PWROK) assertion and NB_RESET# deassertion.

5.PWROK must be monotonic and meet the timing requirements as defined in Table 12, “General AC and DC Characteristics,” on page 32. The processor should not switch between the ring oscillator and the PLL after the initial assertion of PWROK.

6.NB_RESET# must be asserted (causing CONNECT to also assert) before RESET# is deasserted. In practice all Southbridges enforce this requirement.

If NB_RESET# does not assert until after RESET# has deasserted, the processor misinterprets the CONNECT assertion (due to NB_RESET# being asserted) as the beginning of the SIP transfer. There must be sufficient overlap in the resets to ensure that CONNECT is sampled asserted by the processor before RESET# is deasserted.

7.The FID[3:0] signals are valid within 100 ns after PWROK is asserted. The chipset must not sample the FID[3:0] signals until they become valid. Refer to the AMD Athlon™ Processor-Based Motherboard Design Guide, order# 24363, for the specific implementation and additional circuitry required.

8.The FID[3:0] signals become valid within 100 ns after RESET# is asserted. Refer to the AMD Athlon™ Processor- Based Motherboard Design Guide, order# 24363, for the specific implementation and additional circuitry required.

Chapter 8

Signal and Power-Up Requirements

41

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Contents Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet List of Figures Typical AMD Sempron Processor Model 10 System Block DiagramViii List of Tables List of Tables Date Rev Description Revision HistoryXii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Overview Interface SignalsSignaling Technology Push-Pull PP Drivers AMD Athlon System Bus SignalsProcessor Model Logic Symbol DiagramFrequency Control Front-Side Bus Autodetect Legacy DiodeAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management States Power ManagementHalt State Working StateChapter Power Management Connect Protocol Probe StateAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Connect State DiagramDisconnect request Connect Pending Disconnect Disconnect4/CReturn internal clocks to full speed and assert NorthbridgeClock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Duty Cycle Parameter Description Minimum MaximumClock Frequency 333 FSB AMD Athlon System Bus AC Characteristics FSB AMD Athlon System Bus DC Characteristics 333 FSB AMD Athlon System Bus DC CharacteristicsInterface Signal Groupings Interface Signal GroupingsElectrical Data ConventionsVoltage Identification VID40 VID40 DC CharacteristicsFID30 DC Characteristics Vcca AC and DC CharacteristicsFrequency Identification FID30 DecouplingVcccore AC and DC Characteristics Vcccore CharacteristicsVcccore Voltage Waveform Absolute Ratings Absolute RatingsSysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC CharacteristicsGeneral AC and DC Characteristics General AC and DC CharacteristicsSignal Rise Time Sync Input Setup TimeSignal Fall Time Sync Input Hold Time50 Ω ±3% Open-Drain Pin IOL = Output Current2 Open Drain Test CircuitCharacteristics Thermal Diode CharacteristicsThermal Diode Electrical Characteristics Thermal DiodeAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Guidelines for Platform Thermal Protection of the Processor Apic Pins AC and DC CharacteristicsApic Pin AC and DC Characteristics Hold Time Setup TimePower-Up Requirements Signal and Power-Up RequirementsPwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Selection FID30 Processor Warm Reset RequirementsClock Multiplier Die Loading Mechanical DataMechanical Loading Location Dynamic MAX Static MAX Units Die Surface 100453 Letter or Minimum MaximumChapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Descriptions Pin Diagram and Pin Name AbbreviationsModel AMD Sempron Processor AMD Sempron Processor Model 10 Pin Diagram-Bottomside ViewPin Name Abbreviations AA31 Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33AC31 AD30AJ35 AE33AG37 AL33J35 W33E27 E15F28 F24F32 F34AK36 AK34AM10 AM14V32 V30V34 V36Pin List Pin Name Cross-Reference by Pin LocationNo Pin A35 SDATA40# A37 SDATA30#E29 SDATA33# E31 SDATA32# Pin Name SDATA52# E11 SDATA50# E13 SDATA49# E15E33 NC Pin E35 SDATA31# E37 SDATA22# NC Pin F10H28 NC Pin H30 H32 H34 NC Pin H10 H12NC Pin VID4 J31 J33 SDATA19# J35 J37 SDATA29#S31 NC Pin S33 Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16#S35 SDATA15# S37 U31 NC Pin U33NC Pin W31 W33 FID0 FID1FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 Y37 SDATA12#AE31 NC Pin AE33 NC Pin AD30 AD32NC Pin AF10 AF12 AF20NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 AH30 FSBSense1 AH32AJ27 NC Pin AJ29 NC Pin AK10NC Pin AM10 AL25 NC Pin AL27 AL29NC Pin AN11 AN13 AN25 NC Pin AN27 AN29Detailed Pin Descriptions COREFB# Pins Sysclk PinsPins Connect PinFID30 Clock Multiplier Encodings FID30 PinsFLUSH# Pin Front-Side Bus Sense Truth TableIGNNE# Pin INIT# PinK7CLKOUT# Pins Jtag PinsKey Pins NC PinsScan Pins SADDOUT10# PinsThermdc Pins Pwrok PinVID40 Code to Voltage Definition VID40 PinsVrefsys Pin ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Standard AMD Sempron Processor Model 10 Products Ordering InformationAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Constants and Variables for the Ideal Diode Equation Ideal Diode EquationTemperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Appendix B Signals and BitsData Terminology Abbreviation Meaning Abbreviations and AcronymsAbbreviations API AcronymsNMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet
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