AMD 10 manual Processor Warm Reset Requirements, Clock Multiplier, Selection FID30

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AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet

31994A—1 August 2004

Clock Multiplier	The chipset samples the FID[3:0] signals in a chipset-specific
Selection (FID[3:0])	manner from the processor and uses this information to
	determine the correct serial initialization packet (SIP). The
	chipset then sends the SIP information to the processor for
	configuration of the AMD Athlon system bus for the clock
	multiplier that determines the processor frequency indicated
	by the FID[3:0] code. The SIP is sent to the processor using the
	SIP protocol. This protocol uses the PROCRDY, CONNECT, and
	CLKFWDRST signals, that are synchronous to SYSCLK.
	For more information about FID[3:0], see “FID[3:0] Pins” on
	page 70.
	Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
	AMD Duron™ System Bus Specification, order# 21902 for details
	of the SIP protocol.

8.2Processor Warm Reset Requirements

Northbridge Reset RESET# cannot be asserted to the processor without also being

Pinsasserted to the Northbridge. RESET# to the Northbridge is the same as PCI RESET#. The minimum assertion for PCI RESET# is one millisecond. Southbridges enforce a minimum assertion of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0 milliseconds.

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Signal and Power-Up Requirements

Chapter 8

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Contents Data Sheet Advanced Micro Devices, Inc. All rights reserved Table of Contents Mechanical Data Ordering Information AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Typical AMD Sempron Processor Model 10 System Block Diagram List of FiguresViii List of Tables List of Tables Revision History Date Rev DescriptionXii Overview Chapter QuantiSpeed Architecture Summary Typical AMD Sempron Processor Model 10 System Block Diagram Interface Signals Signaling TechnologyOverview AMD Athlon System Bus Signals Push-Pull PP DriversFrequency Control Front-Side Bus Autodetect Legacy Logic Symbol DiagramProcessor Model DiodeAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Power Management Power Management StatesWorking State Halt StateChapter Power Management Probe State Connect ProtocolAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Procrdy Exiting the Stop Grant State and Bus Connect Sequence Diagram Connect StateReturn internal clocks to full speed and assert Connect Pending Disconnect Disconnect4/CDisconnect request NorthbridgeClock Control Cpuid Support AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet 256K L2 Cache Specifications Parameter Description Minimum Maximum Clock FrequencyDuty Cycle 333 FSB AMD Athlon System Bus AC Characteristics 333 FSB AMD Athlon System Bus DC Characteristics FSB AMD Athlon System Bus DC CharacteristicsElectrical Data Interface Signal GroupingsInterface Signal Groupings ConventionsVID40 DC Characteristics Voltage Identification VID40Frequency Identification FID30 Vcca AC and DC CharacteristicsFID30 DC Characteristics DecouplingVcccore Characteristics Vcccore AC and DC CharacteristicsVcccore Voltage Waveform Absolute Ratings Absolute RatingsSysclk and SYSCLK# DC Characteristics Sysclk and SYSCLK# DC CharacteristicsGeneral AC and DC Characteristics General AC and DC CharacteristicsSignal Fall Time Sync Input Setup TimeSignal Rise Time Sync Input Hold TimeOpen Drain Test Circuit 50 Ω ±3% Open-Drain Pin IOL = Output Current2Thermal Diode Electrical Characteristics Thermal Diode CharacteristicsCharacteristics Thermal DiodeAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Apic Pins AC and DC Characteristics Apic Pin AC and DC CharacteristicsGuidelines for Platform Thermal Protection of the Processor Setup Time Hold TimeSignal and Power-Up Requirements Power-Up RequirementsPwrok AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Processor Warm Reset Requirements Clock MultiplierSelection FID30 Mechanical Loading Mechanical DataDie Loading Location Dynamic MAX Static MAX Units Die Surface 100Letter or Minimum Maximum 453Chapter Mechanical Data Dimension 49.27 49.78 D1/E1 45.72 BSC 917 REF 42 REF 977 Chapter Mechanical Data AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Pin Diagram and Pin Name Abbreviations Pin DescriptionsModel AMD Sempron Processor Model 10 Pin Diagram-Bottomside View AMD Sempron ProcessorPin Name Abbreviations AC31 Abbreviation Full Name Pin Q31 S31 U31 U37 W31 Y31 Y33AA31 AD30AG37 AE33AJ35 AL33E27 W33J35 E15F32 F24F28 F34AM10 AK34AK36 AM14V34 V30V32 V36Pin List No Pin Cross-Reference by Pin LocationPin Name A35 SDATA40# A37 SDATA30#E33 NC Pin E35 SDATA31# E37 SDATA22# SDATA52# E11 SDATA50# E13 SDATA49# E15E29 SDATA33# E31 SDATA32# Pin Name NC Pin F10NC Pin VID4 J31 J33 SDATA19# J35 NC Pin H10 H12H28 NC Pin H30 H32 H34 J37 SDATA29#S35 SDATA15# S37 Key Pin Q31 NC Pin Q33 SDATA24# Q35 SDATA17# Q37 SDATA16#S31 NC Pin S33 U31 NC Pin U33FID2 FID3 NC Pin Key Pin Y31 Y33 Y35 FID0 FID1NC Pin W31 W33 Y37 SDATA12#NC Pin AF10 AF12 NC Pin AD30 AD32AE31 NC Pin AE33 AF20AJ27 NC Pin AJ29 AH30 FSBSense1 AH32NC Pin AJ11 AJ13 Analog AJ15 AJ17 AJ19 AJ21 NC Pin AK10NC Pin AN11 AN13 AL25 NC Pin AL27 AL29NC Pin AM10 AN25 NC Pin AN27 AN29Detailed Pin Descriptions Pins Sysclk PinsCOREFB# Pins Connect PinFID30 Pins FID30 Clock Multiplier EncodingsIGNNE# Pin Front-Side Bus Sense Truth TableFLUSH# Pin INIT# PinKey Pins Jtag PinsK7CLKOUT# Pins NC PinsThermdc Pins SADDOUT10# PinsScan Pins Pwrok PinVID40 Pins Vrefsys PinVID40 Code to Voltage Definition ZN and ZP Pins AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ordering Information Standard AMD Sempron Processor Model 10 ProductsAMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Ideal Diode Equation Constants and Variables for the Ideal Diode EquationTemperature Offset Correction ⎛--- I-- high------ ⎞ AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet Signals and Bits Appendix BData Terminology Abbreviations and Acronyms AbbreviationsAbbreviation Meaning Acronyms APINMI VGA Related Publications AMD Sempron Processor Model 10 with 256K L2 Cache Data Sheet

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