31994A | AMD Sempron™ Processor Model 10 with 256K L2 Cache Data Sheet |
PWROK Pin | The PWROK input to the processor must not be asserted until | |
| all voltage planes in the system are within specification and all | |
| system clocks are running within specification. |
|
| For more information, Chapter 8, “Signal and | |
| Requirements” on page 39. |
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SADDIN[1:0]# and | The AMD Sempron processor model 10 does not support | |
SADDOUT[1:0]# Pins | SADDIN[1:0]# or SADDOUT[1:0]#. SADDIN[1]# is tied to VCC | |
| with pullup resistors, if this bit is not supported by the | |
| Northbridge (future models can support SADDIN[1]#). | |
| SADDOUT[1:0]# are tied to VCC with pullup resistors if these | |
| pins are supported by the Northbridge. For more information, | |
| see the A M D Athlon™ and AMD Duron™ System Bus | |
| Specification, order# 21902. |
|
Scan Pins | SCANSHIFTEN, SCANCLK1, SCANINTEVAL, and SCANCLK2 | |
| are the scan interface. This interface is AMD internal and is | |
| tied disabled with pulldown resistors to ground on the | |
| motherboard. |
|
SMI# Pin | SMI# is an input that causes the processor to enter the system | |
| management mode. |
|
STPCLK# Pin | STPCLK# is an input that causes the processor to enter a lower | |
| power mode and issue a Stop Grant special cycle. |
|
SYSCLK and SYSCLK# | SYSCLK and SYSCLK# are differential input clock signals | |
| provided to the PLL of the processor from a | |
| generator. |
|
| See “CLKIN, RSTCLK (SYSCLK) Pins” on page 69 for more | |
| information. |
|
THERMDA and | Thermal Diode anode and cathode pins are used to monitor the | |
THERMDC Pins | actual temperature of the processor die, providing more | |
| accurate temperature control to the system. |
|
| See Table 13, “Thermal Diode Electrical Characteristics,” on | |
| page 35 for more information. |
|
VCCA Pin | VCCA is the processor PLL supply. For information about the | |
| VCCA pin, see Table 5, “VCCA AC and DC Characteristics,” on | |
| page 35 and the AMD Athlon™ | |
| Design Guide, order# 24363. |
|
| To prevent damage to the processor, do not pull this signal High | |
| above 2.5 V. Do not expose this pin to a differential voltage | |
| greater than 1.60 V, relative to the processor core voltage. |
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Chapter 10 | Pin Descriptions | 73 |