Analog Devices ADSP-2186 specifications Parameter Min Max Clock Signals and Reset, Control Signals

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ADSP-2186

TIMING PARAMETERS

Parameter							Min	Max
Clock Signals and Reset
Timing Requirements:
tCKI	CLKIN Period						60 [50]	150
tCKIL	CLKIN Width Low						20
tCKIH	CLKIN Width High						20
Switching Characteristics:
tCKL	CLKOUT Width Low						0.5 tCK – 7
tCKH	CLKOUT Width High						0.5 tCK – 7
tCKOH	CLKIN High to CLKOUT High						0	20
Control Signals
Timing Requirements:
tRSP	RESET	Width Low1					5 tCK
tMS	Mode Setup Before			RESET		High	2
tMH	Mode Setup After		RESET		High		5

Unit

ns ns ns

NOTES

Parameters displayed inside brackets [ ] represent preliminary 40 MHz specifications.

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal oscillator start-up time).

CLKIN

tCKI

tCKIL

tCKIH

tCKOH

tCKH

CLKOUT

PF(2:0)*

RESET

tMS

tCKL

tMH

*PF2 IS MODE C, PF1 IS MODE B, PF0 IS MODE A

Figure 14. Clock Signals

REV. 0

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Image 17

Contents General Description Functional Block DiagramGeneral Note Architecture Overview Development SystemAdditional Information PIN Descriptions Serial PortsCommon-Mode Pins Input Pin Name Pins Output FunctionMemory Interface Pins Setting Memory ModePower-Down LOW Power OperationSource Of Interrupt Interrupt Vector Address Hex InterruptsIdle Idle nSlow Idle System InterfaceReset Clock SignalsMemory Architecture Program MemoryMemory A13 A120 Space Full Memory ModeAddress Range Wait State Register Data MemoryInternal Memory DMA Port Idma Port Host Memory Mode Byte Memory DMA BDMA, Full Memory ModeInternal Memory Space Word Size AlignmentBooting Method Syntax IOaddr = dreg dreg = IOaddr MR Value Biased Unbiased Before RND RND ResultBiased Rounding Designing AN EZ-ICE*-COMPATIBLE SystemTarget System Interface Signals Target Board Connector for EZ-ICE* ProbeTarget Memory Interface PM, DM, BM, IOM, & CMGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Power Dissipation Total Power Dissipation = Pint + C × VDD2 × fPackage AssumptionsOutput Enable Time Output Disable TimeCapacitive Loading Test ConditionsControl Signals Parameter Min Max Clock Signals and ResetFlag Output Delay from Clkout Low5 TCK + IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle IAD15-0 Data Setup before End of Write2, 3Iack Low before Start of Write1 Duration of Write1Parameter Min Max Unit Idma Write, Long Write Cycle IAD15-0 Data Setup beforeLow before Start of Write1 Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle High after Start of Read1 Duration of Read Switching CharacteristicsParameter Min Max Unit Idma Read, Short Read Cycle ADSP-2186 Lead Tqfp Package PinoutNumber Name A4/IAD3 PinA5/IAD4 A6/IAD5ST-100 Outline DimensionsOrdering Guide Page C2999-6-3/97