Analog Devices ADSP-2186 specifications Lead Tqfp Package Pinout

Page 28

ADSP-2186

100-Lead TQFP Package Pinout

A4/IAD3 1 A5/IAD4 2 GND 3 A6/IAD5 4 A7/IAD6 5 A8/IAD7 6 A9/IAD8 7 A10/IAD9 8 A11/IAD10 9 A12/IAD11 10

A13/IAD12 11

GND 12

CLKIN 13

XTAL 14

VDD 15

CLKOUT 16

GND 17

VDD 18

WR 19

RD 20

BMS 21

DMS 22

PMS 23

IOMS 24

CMS 25

A3/IAD2		A2/IAD1		A1/IAD0		A0		PWDACK		BGH		PF0 [MODE A]		PF1 [MODE B]		GND	PWD			VDD		PF2 [MODE C]		PF3		FL0		FL1		FL2		D23		D22		D21		D20		GND		D19		D18		D17		D16
100		99		98		97		96		95		94		93		92		91		90		89		88		87		86		85		84		83		82		81		80		79		78		77		76

PIN 1

IDENTIFIER

ADSP-2186

TOP VIEW

(Not to Scale)

26		27		28		29		30		31		32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50

IRQE+PF4		IRQL0+PF5		GND		IRQL1+PF6		IRQ2+PF7		DT0		TFS0		RFS0		DR0		SCLK0		VDD		DT1		TFS1		RFS1		DR1		GND		SCLK1		ERESET		RESET	EMS			EE		ECLK		ELOUT		ELIN		EINT

75D15

74D14

73D13

72D12

71GND

70D11

69D10

68D9

67VDD

66GND

65D8

64D7/IWR

63D6/IRD

62D5/IAL

61D4/IS

60GND

59VDD

58D3/IACK

57D2/IAD15

56D1/IAD14

55D0/IAD13

54BG

53EBG

52BR

51EBR

–28–

REV. 0

Image 28

Contents General Note Functional Block DiagramGeneral Description Additional Information Development SystemArchitecture Overview Serial Ports PIN DescriptionsInput Pin Name Pins Output Function Common-Mode PinsMemory Interface Pins Setting Memory ModeLOW Power Operation Power-DownSource Of Interrupt Interrupt Vector Address Hex InterruptsIdle n IdleSlow Idle System InterfaceClock Signals ResetMemory Architecture Program MemorySpace Full Memory Mode Memory A13 A120Address Range Wait State Register Data MemoryByte Memory DMA BDMA, Full Memory Mode Internal Memory DMA Port Idma Port Host Memory ModeInternal Memory Space Word Size AlignmentBooting Method MR Value Biased Unbiased Before RND RND Result Syntax IOaddr = dreg dreg = IOaddrBiased Rounding Designing AN EZ-ICE*-COMPATIBLE SystemTarget Board Connector for EZ-ICE* Probe Target System Interface SignalsTarget Memory Interface PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Typ Max UnitWR Low Total Power Dissipation = Pint + C × VDD2 × f Power DissipationPackage AssumptionsOutput Disable Time Output Enable TimeCapacitive Loading Test ConditionsParameter Min Max Clock Signals and Reset Control SignalsIRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK + Flag Output Delay from Clkout Low5 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch IAD15-0 Data Setup before End of Write2, 3 Parameter Min Max Idma Write, Short Write CycleIack Low before Start of Write1 Duration of Write1IAD15-0 Data Setup before Parameter Min Max Unit Idma Write, Long Write CycleLow before Start of Write1 Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle Duration of Read Switching CharacteristicsHigh after Start of Read1 Lead Tqfp Package Pinout ADSP-2186Pin Number Name A4/IAD3A5/IAD4 A6/IAD5Ordering Guide Outline DimensionsST-100 Page C2999-6-3/97