Clock Signals
The ADSP-2186 can be clocked by either a crystal or a TTL- compatible clock signal.
The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’s Manual, for detailed information on this power-down feature.
If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is con- nected to the processor’s CLKIN input. When an external clock is used, the XTAL input must be left unconnected.
The ADSP-2186 uses an input clock with a frequency equal to half the instruction rate; a 16.67 MHz input clock yields a 30 ns processor cycle (which is equivalent to 33 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled.
Because the ADSP-2186 includes an on-chip oscillator circuit, an external crystal may be used. The crystal should be con- nected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 3. Capacitor values are dependent on crystal type and should be specified by the crystal manufac- turer. A parallel-resonant, fundamental frequency, microproces- sor-grade crystal should be used.
A clock output (CLKOUT) signal is generated by the proces- sor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register.
CLKIN XTAL CLKOUT
DSP
Figure 3. External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-2186. The RESET signal must be asserted during the power-up
sequence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the mini-
mum pulse width specification, tRSP.
The RESET input contains some hysteresis; however, if you use an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the boot-loading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes.
MEMORY ARCHITECTURE
The ADSP-2186 provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory and I/O.
Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-2186 has 8K words of Program Memory RAM on chip, and the capabil- ity of accessing up to two 8K external memory overlay spaces using the external data bus. Both an instruction opcode and a data value can be read from on-chip program memory in a single cycle.
Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memory-mapped control registers. The ADSP-2186 has 8K words on Data Memory RAM on chip, consisting of 8160 user-accessible locations and 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus.
Byte Memory (Full Memory Mode) provides access to an
8-bit wide memory space through the Byte DMA (BDMA) port. The Byte Memory interface provides access to 4 MBytes of memory by utilizing eight data lines as additional address lines. This gives the BDMA Port an effective 22-bit address range. On power-up, the DSP can automatically load bootstrap code from byte memory.
I/O Space (Full Memory Mode) allows access to 2048 loca- tions of 16-bit-wide data. It is intended to be used to communi- cate with parallel peripheral devices such as data converters and external registers or latches.
Program Memory
The ADSP-2186 contains an 8K × 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2186 allows the use of 8K external memory overlays.
The program memory space organization is controlled by the Mode B pin and the PMOVLAY register. Normally, the ADSP- 2186 is configured with Mode B = 0 and program memory organized as shown in Figure 4.
PROGRAM MEMORY | ADDRESS |
| 0x3FFF |
EXTERNAL 8K
(PMOVLAY = 1 or 2,
MODE B = 0)
0x2000
0x1FFF
8K INTERNAL
0x0000
Figure 4. Program Memory (Mode B = 0)
