Analog Devices ADSP-2186 specifications Parameter Min Max Unit Bus Request/Grant

Page 19

ADSP-2186

Parameter

Min

Max

Unit

Bus Request/Grant

Timing Requirements:

tBH

BR

Hold after CLKOUT High1

0.25 tCK + 2

ns

tBS

BR Setup before CLKOUT Low1

0.25 tCK + 17

ns

Switching Characteristics:

tSD

CLKOUT High to

xMS

,

RD

,

WR

Disable

0.25 tCK + 10

ns

tSDB

xMS, RD, WR Disable to BG Low

0

ns

tSE

BG

High to

xMS

,

RD

,

WR

Enable

0

ns

tSEC

xMS

,

RD

,

WR

Enable to CLKOUT High

0.25 tCK – 7

ns

tSDBH

xMS, RD, WR Disable to BGH Low2

0

ns

tSEH

BGH

High to

xMS

,

RD

,

WR

Enable2

0

ns

NOTES

xMS = PMS, DMS, CMS, IOMS, BMS.

1BR is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships.

2BGH is asserted when the bus is granted and the processor requires control of the bus to continue.

CLKOUT

BR

CLKOUT

PMS, DMS BMS, RD WR

BG

BGH

tBH

tBS

tSD

tSDB

tSDBH

tSEC

tSE

tSEH

Figure 16. Bus Request–Bus Grant

REV. 0

–19–

Image 19

Contents General Note Functional Block DiagramGeneral Description Additional Information Development SystemArchitecture Overview PIN Descriptions Serial PortsSetting Memory Mode Input Pin Name Pins Output FunctionCommon-Mode Pins Memory Interface PinsInterrupts LOW Power OperationPower-Down Source Of Interrupt Interrupt Vector Address HexSystem Interface Idle nIdle Slow IdleProgram Memory Clock SignalsReset Memory ArchitectureData Memory Space Full Memory ModeMemory A13 A120 Address Range Wait State RegisterMemory Space Word Size Alignment Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode InternalBooting Method Designing AN EZ-ICE*-COMPATIBLE System MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Biased RoundingPM, DM, BM, IOM, & CM Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals Target Memory InterfaceGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Assumptions Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation PackageTest Conditions Output Disable TimeOutput Enable Time Capacitive LoadingControl Signals Parameter Min Max Clock Signals and ResetFlag Output Hold after Clkout Low5 25 tCK IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Parameter Min Max Unit Interrupts and FlagParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Duration of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Iack Low before Start of Write1Low4 TCK IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low before Start of Write1Parameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle Duration of Read Switching CharacteristicsHigh after Start of Read1 ADSP-2186 Lead Tqfp Package PinoutA6/IAD5 PinNumber Name A4/IAD3 A5/IAD4Ordering Guide Outline DimensionsST-100 Page C2999-6-3/97