Analog Devices ADSP-2186 specifications Grade Parameter Min Max Unit

ADSP-2186 SPECIFICATIONS					ADSP-2186
RECOMMENDED OPERATING CONDITIONS
		K Grade		B Grade
Parameter	Min	Max	Min	Max		Unit
VDD	4.5	5.5	4.5	5.5		V
TAMB	0	+70	–40	+85		°C

ELECTRICAL CHARACTERISTICS

				K/B Grades
Parameter		Test Conditions	Min	Typ	Max	Unit
VIH	Hi-Level Input Voltage1, 2	@ VDD = max	2.0			V
VIH	Hi-Level CLKIN Voltage	@ VDD = max	2.2			V
VIL	Lo-Level Input Voltage1, 3	@ VDD = min			0.8	V
VOH	Hi-Level Output Voltage1, 4, 5	@ VDD = min
		IOH = –0.5 mA	2.4			V
		@ VDD = min
VOL	Lo-Level Output Voltage1, 4, 5	IOH = –100 μA6	VDD – 0.3			V
		@ VDD = min
IIH	Hi-Level Input Current3	IOL = 2 mA			0.4	V
		@ VDD = max				μA
IIL	Lo-Level Input Current3	VIN = VDDmax			10
		@ VDD = max				μA
IOZH	Three-State Leakage Current7	VIN = 0 V			10
		@ VDD = max				μA
IOZL	Three-State Leakage Current7	VIN = VDDmax8			10
		@ VDD = max				μA
IDD	Supply Current (Idle)9	VIN = 0 V8			10
		@ VDD = 5.0		12.4		mA
IDD	Supply Current (Dynamic)10	@ VDD = 5.0
		TAMB = +25°C
		tCK = 30 ns11		55		mA
CI	Input Pin Capacitance3, 6, 12	tCK = 25 ns11		[65]		mA
		@ VIN = 2.5 V,
		fIN = 1.0 MHz,			8	pF
CO	Output Pin Capacitance6, 7, 12, 13	TAMB = +25°C
		@ VIN = 2.5 V,
		fIN = 1.0 MHz,
		TAMB = +25°C			8	pF

Parameters displayed inside brackets, [ ], represent preliminary 40 MHz specifications.

NOTES

1Bidirectional pins: D0-D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1-A13, PF0-PF7.

2Input only pins: RESET, BR, DR0, DR1, PWD.

3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2-0, BGH.

5 Although specified for TTL outputs, all ADSP-2186 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.

6Guaranteed but not tested.

7Three-statable pins: A0-A13, D0-D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RSF1, PF0–PF7.

80 V on BR, CLKIN Inactive.

9Idle refers to ADSP-2186 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.

10IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are type 2 and type 6, and 20% are idle instructions.

11VIN = 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.

12Applies to TQFP package type.

13Output pin capacitance is the capacitive load for any three-stated output pin.

Specifications subject to change without notice.

REV. 0 –13–