Analog Devices ADSP-2186 specifications Parameter Min Max Unit Memory Write

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ADSP-2186

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Memory Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Characteristics:

 

 

 

tDW

Data Setup before

WR

High

0.5 tCK – 7+ w

 

ns

tDH

Data Hold after WR High

0.25 tCK – 2

 

ns

tWP

WR

Pulse Width

0.5 tCK – 5 + w

 

ns

tWDE

WR

Low to Data Enabled

0

 

ns

tASW

A0-A13,

xMS

 

Setup before

WR

Low

0.25 tCK – 6

 

ns

tDDR

Data Disable before

WR

or

RD

Low

0.25 tCK – 7

 

ns

tCWR

CLKOUT High to

WR

 

Low

0.25 tCK – 5

0.25 tCK + 7

ns

tAW

A0-A13, xMS, Setup before

WR

Deasserted

0.75 tCK – 9 + w

 

ns

tWRA

A0-A13,

xMS

Hold after

WR

Deasserted

0.25 tCK – 3

 

ns

tWWR

WR

High to

RD

or

WR

Low

0.5 tCK – 5

 

ns

w = wait states × tCK.

xMS = PMS, DMS, CMS, IOMS, BMS.

CLKOUT

A0–A13

DMS, PMS,

BMS, CMS,

IOMS

WR

D

RD

tASW

tCWR

 

tWRA

 

 

tWP

tWWR

tAW

tDH

tDDR

 

tDW tWDE

Figure 18. Memory Write

REV. 0

–21–

Image 21
Contents Functional Block Diagram General NoteGeneral Description Development System Additional InformationArchitecture Overview PIN Descriptions Serial PortsCommon-Mode Pins Input Pin Name Pins Output FunctionMemory Interface Pins Setting Memory ModePower-Down LOW Power OperationSource Of Interrupt Interrupt Vector Address Hex InterruptsIdle Idle nSlow Idle System InterfaceReset Clock SignalsMemory Architecture Program MemoryMemory A13 A120 Space Full Memory ModeAddress Range Wait State Register Data MemoryInternal Memory DMA Port Idma Port Host Memory Mode Byte Memory DMA BDMA, Full Memory ModeInternal Memory Space Word Size AlignmentBooting Method Syntax IOaddr = dreg dreg = IOaddr MR Value Biased Unbiased Before RND RND ResultBiased Rounding Designing AN EZ-ICE*-COMPATIBLE SystemTarget System Interface Signals Target Board Connector for EZ-ICE* ProbeTarget Memory Interface PM, DM, BM, IOM, & CMGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Power Dissipation Total Power Dissipation = Pint + C × VDD2 × fPackage AssumptionsOutput Enable Time Output Disable TimeCapacitive Loading Test ConditionsControl Signals Parameter Min Max Clock Signals and ResetFlag Output Delay from Clkout Low5 TCK + IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle IAD15-0 Data Setup before End of Write2, 3Iack Low before Start of Write1 Duration of Write1Parameter Min Max Unit Idma Write, Long Write Cycle IAD15-0 Data Setup beforeLow before Start of Write1 Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle Duration of Read Switching Characteristics Parameter Min Max Unit Idma Read, Short Read CycleHigh after Start of Read1 ADSP-2186 Lead Tqfp Package PinoutNumber Name A4/IAD3 PinA5/IAD4 A6/IAD5Outline Dimensions Ordering GuideST-100 Page C2999-6-3/97