Analog Devices ADSP-2186 Pin, Number Name A4/IAD3, A5/IAD4, A6/IAD5, A7/IAD6, D0/IAD13, A8/IAD7

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ADSP-2186

The ADSP-2186 package pinout is shown in the table below. Pin names in bold text replace the plain text named functions when

Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET.

TQFP Pin Configurations

TQFP	Pin	TQFP		Pin		TQFP	Pin	TQFP	Pin
Number	Name	Number	Name			Number	Name	Number	Name

1	A4/IAD3	26		IRQE + PF4		51	EBR	76	D16
2	A5/IAD4	27		IRQL0 + PF5		52	BR	77	D17
3	GND	28		GND		53	EBG	78	D18
4	A6/IAD5	29		IRQL1 + PF6		54	BG	79	D19
5	A7/IAD6	30		IRQ2 + PF7		55	D0/IAD13	80	GND
6	A8/IAD7	31		DT0		56	D1/IAD14	81	D20
7	A9/IAD8	32		TFS0		57	D2/IAD15	82	D21
8	A10/IAD9	33		RFS0		58	D3/IACK	83	D22
9	A11/IAD10	34		DR0		59	VDD	84	D23
10	A12/IAD11	35		SCLK0		60	GND	85	FL2
11	A13/IAD12	36		VDD		61	D4/IS	86	FL1
12	GND	37		DT1		62	D5/IAL	87	FL0
13	CLKIN	38		TFS1		63	D6/IRD	88	PF3
14	XTAL	39		RFS1		64	D7/IWR	89	PF2 [Mode C]
15	VDD	40		DR1		65	D8	90	VDD
16	CLKOUT	41		GND		66	GND	91	PWD
17	GND	42		SCLK1		67	VDD	92	GND
18	VDD	43		ERESET		68	D9	93	PF1 [Mode B]
19	WR	44		RESET		69	D10	94	PF0 [Mode A]
20	RD	45		EMS		70	D11	95	BGH
21	BMS	46		EE		71	GND	96	PWDACK
22	DMS	47		ECLK		72	D12	97	A0
23	PMS	48		ELOUT		73	D13	98	A1/IAD0
24	IOMS	49		ELIN		74	D14	99	A2/IAD1
25	CMS	50		EINT		75	D15	100	A3/IAD2

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Contents General Description Functional Block DiagramGeneral Note Architecture Overview Development SystemAdditional Information PIN Descriptions Serial PortsCommon-Mode Pins Input Pin Name Pins Output FunctionMemory Interface Pins Setting Memory ModePower-Down LOW Power OperationSource Of Interrupt Interrupt Vector Address Hex InterruptsIdle Idle nSlow Idle System InterfaceReset Clock SignalsMemory Architecture Program MemoryMemory A13 A120 Space Full Memory ModeAddress Range Wait State Register Data MemoryInternal Memory DMA Port Idma Port Host Memory Mode Byte Memory DMA BDMA, Full Memory ModeInternal Memory Space Word Size AlignmentBooting Method Syntax IOaddr = dreg dreg = IOaddr MR Value Biased Unbiased Before RND RND ResultBiased Rounding Designing AN EZ-ICE*-COMPATIBLE SystemTarget System Interface Signals Target Board Connector for EZ-ICE* ProbeTarget Memory Interface PM, DM, BM, IOM, & CMGrades Parameter Test Conditions Min Typ Max Unit Grade Parameter Min Max UnitWR Low Power Dissipation Total Power Dissipation = Pint + C × VDD2 × fPackage AssumptionsOutput Enable Time Output Disable TimeCapacitive Loading Test ConditionsControl Signals Parameter Min Max Clock Signals and ResetFlag Output Delay from Clkout Low5 TCK + IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Parameter Min Max Unit Interrupts and Flag Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Parameter Min Max Idma Write, Short Write Cycle IAD15-0 Data Setup before End of Write2, 3Iack Low before Start of Write1 Duration of Write1Parameter Min Max Unit Idma Write, Long Write Cycle IAD15-0 Data Setup beforeLow before Start of Write1 Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle High after Start of Read1 Duration of Read Switching CharacteristicsParameter Min Max Unit Idma Read, Short Read Cycle ADSP-2186 Lead Tqfp Package PinoutNumber Name A4/IAD3 PinA5/IAD4 A6/IAD5ST-100 Outline DimensionsOrdering Guide Page C2999-6-3/97