ADSP-2186
Idle
When the
Slow Idle
The IDLE instruction is enhanced on the
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the proces- sor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to in- coming interrupts. The
When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the ADSP-2186, two serial devices, a byte-wide EPROM and optional external program and data overlay memories (mode selectable). Programmable wait state generation allows the processor to
| FULL MEMORY MODE |
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1/2x CLOCK | CLKIN | 14 |
OR |
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CRYSTAL | XTAL |
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| /PF7 |
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| /PF4 |
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| /PF5 |
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| /PF6 |
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| MODE C/PF2 |
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| MODE B/PF1 |
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| MODE A/PF0 |
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| SPORT1 |
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| SCLK1 |
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SERIAL | RFS1 OR |
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TFS1 OR |
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DEVICE |
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DT1 OR FO |
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| DR1 OR FI |
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| SPORT0 |
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| SCLK0 |
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SERIAL | RFS0 |
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DEVICE | TFS0 |
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| DT0 |
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| DR0 |
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| HOST MEMORY MODE |
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1/2x CLOCK | CLKIN | 1 |
OR | ADDR0 |
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CRYSTAL | XTAL |
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| PF3 | 16 |
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| /PF7 |
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| /PF4 |
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| /PF5 |
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| /PF6 |
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| MODE C/PF2 |
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| MODE B/PF1 |
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| MODE A/PF0 |
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| SPORT1 |
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| SCLK1 |
SERIAL |
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| RFS1 OR |
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DEVICE |
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| TFS1 OR |
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| DT1 OR FO |
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| DR1 OR FI |
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SPORT0
SCLK0
SERIAL RFS0
DEVICE TFS0
DT0
DR0
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| IDMA PORT |
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| /D6 |
SYSTEM |
| /D7 |
INTERFACE |
| /D4 |
OR |
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µCONTROLLER | 16 | /D3 |
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| BYTE | |
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DATA | MEMORY | |||
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ADDR |
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DATA | I/O SPACE | |||
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| 2048 LOCATIONS | |
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ADDR | OVERLAY | |||
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DATA | MEMORY | |||
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| TWO 8K | |
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| PM SEGMENTS | |
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| TWO 8K | |
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| DM SEGMENTS | |
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connect easily to slow peripheral devices. The
Figure 2. Basic System Configuration
REV. 0 |