Analog Devices ADSP-2186 specifications Parameter Min Max Unit Serial Ports

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ADSP-2186

TIMING PARAMETERS

Parameter		Min	Max	Unit

Serial Ports
Timing Requirements:
tSCK	SCLK Period	50		ns
tSCS	DR/TFS/RFS Setup before SCLK Low	4		ns
tSCH	DR/TFS/RFS Hold after SCLK Low	7		ns
tSCP	SCLKIN Width	20		ns
Switching Characteristics:
tCC	CLKOUT High to SCLKOUT	0.25 tCK	0.25 tCK + 10	ns
tSCDE	SCLK High to DT Enable	0		ns
tSCDV	SCLK High to DT Valid		15	ns
tRH	TFS/RFSOUT Hold after SCLK High	0		ns
tRD	TFS/RFSOUT Delay from SCLK High		15	ns
tSCDH	DT Hold after SCLK High	0		ns
tTDE	TFS (Alt) to DT Enable	0		ns
tTDV	TFS (Alt) to DT Valid		14	ns
tSCDD	SCLK High to DT Disable		15	ns
tRDV	RFS (Multichannel, Frame Delay Zero) to DT Valid		15	ns

CLKOUT	tCC
tCC	tCC
SCLK		tSCP
		tSCP
	tSCS	tSCH

DR
TFSIN
RFSIN	tRD
	tRD
	tRH
RFSOUT
TFSOUT	tSCDD
	tSCDD
	tSCDV
	tSCDH
	tSCDE
DT
	tTDE
TFSOUT	tTDV
TFSOUT
ALTERNATE
FRAME MODE
RFSOUT	tRDV
MULTICHANNEL MODE,
FRAME DELAY 0
(MFD = 0)	tTDE
	tTDE

tTDV

TFSIN

ALTERNATE

FRAME MODE

tRDV

RFSIN

MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0)

tSCK

tSCP

Figure 19. Serial Ports

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Contents General Note Functional Block DiagramGeneral Description Additional Information Development SystemArchitecture Overview Serial Ports PIN DescriptionsMemory Interface Pins Input Pin Name Pins Output FunctionCommon-Mode Pins Setting Memory ModeSource Of Interrupt Interrupt Vector Address Hex LOW Power OperationPower-Down InterruptsSlow Idle Idle nIdle System InterfaceMemory Architecture Clock SignalsReset Program MemoryAddress Range Wait State Register Space Full Memory ModeMemory A13 A120 Data MemoryInternal Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode Memory Space Word Size AlignmentBooting Method Biased Rounding MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Designing AN EZ-ICE*-COMPATIBLE SystemTarget Memory Interface Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Typ Max UnitWR Low Package Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation AssumptionsCapacitive Loading Output Disable TimeOutput Enable Time Test ConditionsParameter Min Max Clock Signals and Reset Control SignalsParameter Min Max Unit Interrupts and Flag IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Iack Low before Start of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Duration of Write1Low before Start of Write1 IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle Parameter Min Max Unit Idma Read, Short Read Cycle Duration of Read Switching CharacteristicsHigh after Start of Read1 Lead Tqfp Package Pinout ADSP-2186A5/IAD4 PinNumber Name A4/IAD3 A6/IAD5Ordering Guide Outline DimensionsST-100 Page C2999-6-3/97