Analog Devices ADSP-2186 specifications Parameter Min Max Unit Idma Read, Long Read Cycle

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ADSP-2186

TIMING PARAMETERS

Parameter					Min	Max	Unit

IDMA Read, Long Read Cycle
Timing Requirements:
tIKR	IACK	Low before Start of Read1			0		ns
tIRP	Duration of Read1				15		ns
Switching Characteristics:
tIKHR	IACK High after Start of Read1					15	ns
tIKDS	IAD15–0 Data Setup before		IACK	Low	0.5 tCK – 10		ns
tIKDH	IAD15–0 Data Hold after End of Read2				0		ns
tIKDD	IAD15–0 Data Disabled after End of Read2					10	ns
tIRDE	IAD15–0 Previous Data Enabled after Start of Read				0		ns
tIRDV	IAD15–0 Previous Data Valid after Start of Read					15	ns
tIRDH1	IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3				2 tCK – 5		ns
tIRDH2	IAD15–0 Previous Data Hold after Start of Read (PM2)4				tCK	– 5	ns

NOTES

1Start of Read = IS Low and IRD Low.

2End of Read = IS High or IRD High. 3DM read or first half of PM read.

4Second half of PM read.

IACK

tIKHR tIKR

tIRP

IRD

tIRDE

IAD 15–0

DATA

tIRDV

tIRDH

tIKDS

READ

DATA

tIKDH

tIKDD

Figure 23. IDMA Read, Long Read Cycle

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Contents General Description Functional Block DiagramGeneral Note Architecture Overview Development SystemAdditional Information Serial Ports PIN DescriptionsMemory Interface Pins Input Pin Name Pins Output FunctionCommon-Mode Pins Setting Memory ModeSource Of Interrupt Interrupt Vector Address Hex LOW Power OperationPower-Down InterruptsSlow Idle Idle nIdle System InterfaceMemory Architecture Clock SignalsReset Program MemoryAddress Range Wait State Register Space Full Memory ModeMemory A13 A120 Data MemoryInternal Byte Memory DMA BDMA, Full Memory ModeInternal Memory DMA Port Idma Port Host Memory Mode Memory Space Word Size AlignmentBooting Method Biased Rounding MR Value Biased Unbiased Before RND RND ResultSyntax IOaddr = dreg dreg = IOaddr Designing AN EZ-ICE*-COMPATIBLE SystemTarget Memory Interface Target Board Connector for EZ-ICE* ProbeTarget System Interface Signals PM, DM, BM, IOM, & CMGrade Parameter Min Max Unit Grades Parameter Test Conditions Min Typ Max UnitWR Low Package Total Power Dissipation = Pint + C × VDD2 × fPower Dissipation AssumptionsCapacitive Loading Output Disable TimeOutput Enable Time Test ConditionsParameter Min Max Clock Signals and Reset Control SignalsParameter Min Max Unit Interrupts and Flag IRQx FI, or PFx Setup before Clkout Low1, 2, 3 TCK +Flag Output Delay from Clkout Low5 TCK + Flag Output Hold after Clkout Low5 25 tCKParameter Min Max Unit Bus Request/Grant Parameter Min Max Unit Memory Read Parameter Min Max Unit Memory Write Parameter Min Max Unit Serial Ports Parameter Min Max Unit Idma Address Latch Iack Low before Start of Write1 IAD15-0 Data Setup before End of Write2, 3Parameter Min Max Idma Write, Short Write Cycle Duration of Write1Low before Start of Write1 IAD15-0 Data Setup beforeParameter Min Max Unit Idma Write, Long Write Cycle Low4 TCKParameter Min Max Unit Idma Read, Long Read Cycle High after Start of Read1 Duration of Read Switching CharacteristicsParameter Min Max Unit Idma Read, Short Read Cycle Lead Tqfp Package Pinout ADSP-2186A5/IAD4 PinNumber Name A4/IAD3 A6/IAD5ST-100 Outline DimensionsOrdering Guide Page C2999-6-3/97

ADSP-2186

TIMING PARAMETERS

Parameter

Min

Max

Unit

IDMA Read, Long Read Cycle

IACK

IAD15–0 Data Setup before

IACK

IAD15–0 Previous Data Hold after Start of Read (PM2)4

Figure 23. IDMA Read, Long Read Cycle