SUPER MICRO Computer 5014C-MF user manual Appendix B Bios Post Codes

Appendix B: BIOS POST Codes

Appendix B:

BIOS POST Codes

This section lists the POST (Power On Self Testing) Codes for the Award BIOS.

POST (hex)	Defi nition
CFh	Test CMOS R/W functionality
C0h	Early chipset initialization
	- Disable shadow RAM
	- Disable L2 cache (socket 7 or below)
	- Program basic chipset registers

C1h

Detect memory

-Auto detection of DRAM size, type and ECC

-Auto detection of L2 cache (socket 7 or below)

C3h

C5h

0h1

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

Expand compressed BIOS code to DRAM

Call chipset hook to copy BIOS back to E000 & F000 shadow RAM

Expand the Xgroup codes located in physical address 1000:0

Reserved

Initial Superio_Early_Init switch

Reserved

1.Blank out screen

2.Clear CMOS error fl ag

Reserved

1.Clear 8042 interface

2.Initialize 8042 self-test

1.Test special keyboard controller for Winbond 977 series Super I/O chips

2.Enable keyboard interface

Reserved

1.Disable PS/2 mouse interface

2.Auto detect ports for keyboard & mouse followed by a port & interface swap (optional)

3.Reset keyboard for Winbond 977 series Super I/O chips

0Bh

0Ch

0Dh

0Eh

0Fh

10h

11h

Reserved

Reserved

Reserved

Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the speaker.

Reserved

Auto detect fl ash type to load appropriate fl ash R/W codes into the run time area in F000 for ESCD & DMI support

Reserved

B-1