Omega Vehicle Security OME-PIO-D56 manual RESET\ Control Register, AUX Control Register

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3.3.1RESET\ Control Register

(Read/Write): wBase+0

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET\

Note. Refer to Sec. 3.1 for more information about wBase.

When the PC is first powered up, the RESET\ signal is in Low-state. This will disable all D/I/O operations. The user has to set the RESET\ signal to High-state before any D/I/O command.

outportb(wBase,1);	/*	RESET\=High Æ all D/I/O are enable now */
outportb(wBase,0);	/*	RESET\=Low Æ all D/I/O are disable now */

3.3.2AUX Control Register

(Read/Write): wBase+2

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Aux7	Aux6	Aux5	Aux4	Aux3	Aux2	Aux1	Aux0

Note. Refer to Sec. 3.1 for more information about wBase.

Aux?=0Æ this Aux is used as a D/I Aux?=1Æ this Aux is used as a D/O

When the PC is first powered up, All Aux? signals are in Low-state. All Aux? are designed as D/I for all OME-PIO/PISO series. Please set all Aux? in D/I state.

3.3.3AUX data Register

(Read/Write): wBase+3

Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
Aux7	Aux6	Aux5	Aux4	Aux3	Aux2	Aux1	Aux0

Note. Refer to Sec. 3.1 for more information about wBase.

When the Aux? is used as D/O, the output state is controlled by this register. This register is designed and reserved for feature extension, so do not control this register now.

OME-PIO-D56/PIO-D24 User Manual (Ver.2.1, Oct/2003, PPH-005-21)

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Contents User’sGuide Canada MexicoBenelux Czech RepublicOME-PIO-D56/D24 Table of Contents Features IntroductionSpecifications Order DescriptionOptions Product Checklist PCI Data Acquisition FamilyOME-PISO-series cost-effective generation, isolated cards Hardware configuration Board LayoutI/O Port Location Enabling I/O Operation1 DI/DO Port Architecture CON3 Select Sec RESET\ Sec DI Port Architecture CON2 Do Port Architecture CON1 If INT signal is Low now Æ select the non-inverted input Interrupt OperationMake sure the initial level is High or Low Interrupt Block Diagram of OME-PIO D56/D24 Interrupt output signal of OME-PIO-D56/OME-PIO-D24, INT\ isINTCHAN0/1/2/3 Initialhigh, activelow Interrupt source COUNTL++Initiallow, activehigh Interrupt source Muliti-Interrupt Source PC0 PC1 PC2 PC3Read all interrupt state Daughter Boards OME-DB-37OME-DN-37 OME-DB-8125OME-ADP-20/PCI OME-DB-24PD Isolated Input Board OME-DB-24RD Relay Board OME-DB-24PRD, OME-DB-24POR, OME DB-24C Daughter Board Comparison Table All signals are TTL compatible Pin AssignmentDI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 How to Find the I/O Address Resource-allocated informationPIO/PISO identification information PC’s physical slot informationPIODriverInit PIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAuxWSubVendor=0x80 wSubDevice=1 wSubAux=0x40 For D56/D24Printf\nThrer are %d Piopiso Cards in this PC,wBoards OME-PISO-P32C32 PIOGetConfigAddressSpace Enable all D/I/O operations of card0Enable all D/I/O operations of card1 ShowPIOPISO ShowPIOPISOwSubVendor,wSubDevice,wSubAuxAssignment of I/O Address Slot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07I/O Address Map Address Read WriteRESET\ Control Register AUX Control RegisterAUX data Register INT Mask Control Register Aux Status RegisterInterrupt Polarity Control Register 7 I/O Selection Control RegisterRead/Write 8-bit data Register How to install software & utility? Demo programPiopiso PIOPISO.EXE for Windows DEMO1 DEMO2 DEMO3 COUNT=0COUNT++ DEMO4 COUNT++ DEMO5 PC3CNTL1=CNTL2=CNTL3=CNTL4=0 Page WARRANTY/DISCLAIMER Temperature