Omega Vehicle Security OME-PIO-D56 manual I/O Port Location, Enabling I/O Operation

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2.2I/O Port Location

The OME-PIO-D56/OME-PIO-D24 consists of one 24-bit bi-directional port, one

16bit input port and one 16 bit output port (only for OME-PIO-D56). The 24-bit port supports three 8-bit groups: PA, PB & PC. Each 8-bit group can be individually configured to function as either inputs or outputs. All groups using 24-bit bi- directional ports are configured as inputs upon power-up or reset. The I/O port locations are as follows:

Connector of

PA0 ~ PA7

PB0 ~ PB7

PC0 ~ PC7

OME-PIO-D56/D24

 

 

 

 

 

 

CON3 (DI/O)

Port0

 

Port1

Port2

 

 

 

 

 

 

Connector of OME-PIO-D56

 

Description

 

 

 

CON1

 

 

D/O

 

 

 

CON2

 

 

D/I

 

 

 

Refer to Sec. 2.1 for board layout & I/O port location.

Note: PC0, PC1, PC2 and PC3 can be used as interrupt signal source. Refer to Sec. 2.4 for more information.

2.3Enabling I/O Operation

2.3.1DI/DO Port Architecture (CON3)

Upon power-up, all D/I/O port (CON3) operations are disabled. The RESET\ signal controls the enable/disable state of D/I/O port. Refer to Sec. 3.3.1 for more information about RESET\ signal. The power-up states are as follows:

All D/I/O operations are disabled

All three D/I/O ports are configured as D/I port

All D/O latch register are undefined.(refer to Sec. 2.3.2)

Initialization must be performed before using these D/I/Os. The recommended steps are as follows:

Step 1: Find address-mapping of OME-PIO/PISO cards (refer to Sec. 3.1)

Step 2: Enable all D/I/O operations (refer to Sec. 3.3.1)

Step 3: Configure the three ports (in CON3) to their expected D/I/O state & send the initial value to all D/O ports (refer to Sec. 3.3.8)

Refer to DEMO1.C for demo program.

OME-PIO-D56/OME-PIO-D24 User Manual (Ver.2.1, Oct/2003)

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Contents User’sGuide Mexico CanadaBenelux Czech RepublicOME-PIO-D56/D24 Table of Contents Introduction FeaturesSpecifications Order DescriptionOptions Product Checklist PCI Data Acquisition FamilyOME-PISO-series cost-effective generation, isolated cards Board Layout Hardware configurationI/O Port Location Enabling I/O Operation1 DI/DO Port Architecture CON3 Select Sec RESET\ Sec DI Port Architecture CON2 Do Port Architecture CON1 If INT signal is Low now Æ select the non-inverted input Interrupt OperationMake sure the initial level is High or Low Interrupt output signal of OME-PIO-D56/OME-PIO-D24, INT\ is Interrupt Block Diagram of OME-PIO D56/D24INTCHAN0/1/2/3 COUNTL++ Initialhigh, activelow Interrupt sourceInitiallow, activehigh Interrupt source PC0 PC1 PC2 PC3 Muliti-Interrupt SourceRead all interrupt state OME-DB-37 Daughter BoardsOME-DN-37 OME-DB-8125OME-ADP-20/PCI OME-DB-24PD Isolated Input Board OME-DB-24RD Relay Board OME-DB-24PRD, OME-DB-24POR, OME DB-24C Daughter Board Comparison Table Pin Assignment All signals are TTL compatibleDI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 Resource-allocated information How to Find the I/O AddressPIO/PISO identification information PC’s physical slot informationPIODriverInit&wBoards, wSubVendor,wSubDevice,wSubAux PIODriverInitWSubVendor=0x80 wSubDevice=1 wSubAux=0x40 For D56/D24Printf\nThrer are %d Piopiso Cards in this PC,wBoards OME-PISO-P32C32 PIOGetConfigAddressSpace Enable all D/I/O operations of card0Enable all D/I/O operations of card1 ShowPIOPISOwSubVendor,wSubDevice,wSubAux ShowPIOPISOSlot5 0x0A Slot6 0x08 Slot7 0x09 Slot8 0x07 Assignment of I/O AddressAddress Read Write I/O Address MapRESET\ Control Register AUX Control RegisterAUX data Register Aux Status Register INT Mask Control Register7 I/O Selection Control Register Interrupt Polarity Control RegisterRead/Write 8-bit data Register Demo program How to install software & utility?Piopiso PIOPISO.EXE for Windows DEMO1 DEMO2 COUNT=0 DEMO3COUNT++ DEMO4 COUNT++ PC3 DEMO5CNTL1=CNTL2=CNTL3=CNTL4=0 Page WARRANTY/DISCLAIMER Temperature