Cypress CY7C1318BV18, CY7C1320BV18, CY7C1316BV18 manual Parameter Min Max Output Times, DLL Timing

Page 24

CY7C1316BV18, CY7C1916BV18

CY7C1318BV18, CY7C1320BV18

Switching Characteristics (continued)

Over the Operating Range [20, 21]

Cypress

Consortium

 

 

 

 

 

Description

300 MHz

278 MHz

250 MHz

200 MHz

167 MHz

Unit

Parameter

Parameter

 

 

 

 

 

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Times

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCO

tCHQV

C/C

Clock Rise (or K/K in single

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50

ns

 

 

clock mode) to Data Valid

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tDOH

tCHQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Data Output Hold after Output C/C

 

–0.45

–

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

 

 

Clock Rise (Active to Active)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCCQO

tCHCQV

 

 

Clock Rise to Echo Clock Valid

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50

ns

C/C

tCQOH

tCHCQX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Echo Clock Hold after C/C

Clock

–0.45

–

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

 

 

Rise

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCQD

tCQHQV

Echo Clock High to Data Valid

–

0.27

–

0.27

–

0.30

–

0.35

–

0.40

ns

tCQDOH

tCQHQX

Echo Clock High to Data Invalid

–0.27

–

–0.27

–

–0.30

–

–0.35

–

–0.40

–

ns

tCHZ

tCHQZ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock (C/C)

Rise to High-Z

–

0.45

–

0.45

–

0.45

–

0.45

–

0.50

ns

 

 

(Active to High-Z) [24, 25]

 

 

 

 

 

 

 

 

 

 

 

tCLZ

tCHQX1

 

 

 

 

 

Rise to Low-Z [24, 25]

 

 

 

 

 

 

 

 

 

 

 

Clock (C/C)

–0.45

–

–0.45

–

–0.45

–

–0.45

–

–0.50

–

ns

DLL Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tKC Var

tKC Var

Clock Phase Jitter

–

0.20

–

0.20

–

0.20

–

0.20

–

0.20

ns

tKC lock

tKC lock

DLL Lock Time (K, C)

1024

–

1024

–

1024

–

1024

–

1024

–

Cycles

tKC Reset

tKC Reset

K Static to DLL Reset

30

–

30

–

30

–

30

–

30

–

ns

Notes

24.tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms on page 22. Transition is measured ±100 mV from steady-state voltage.

25.At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

Document Number: 38-05621 Rev. *D

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1316BV18 Logic Block Diagram CY7C1916BV18Doff CLKLogic Block Diagram CY7C1318BV18 Logic Block Diagram CY7C1320BV18BWS Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1316BV18 2M x CY7C1916BV18 2M xCY7C1318BV18 1M x CY7C1320BV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Application Example Programmable ImpedanceEcho Clocks SRAM#1 ZQWrite Cycle Descriptions OperationFirst Address External Second Address Internal CommentsWrite cycle description table for CY7C1916BV18 follows Write cycle description table for CY7C1320BV18 followsDevice Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document Number 38-05621 Rev. *D Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms DON’T Care UndefinedOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSYT NXRSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsVKN/PYRS USB

CY7C1316BV18, CY7C1916BV18, CY7C1320BV18, CY7C1318BV18 specifications

The Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 are advanced synchronous static RAM (SRAM) devices designed to meet the high-performance requirements of modern computing systems. Offering a blend of high speed, low power consumption, and large storage capacities, these chips are widely utilized in applications such as networking equipment, telecommunications, and high-speed data processing.

The CY7C1318BV18 is a 2 Megabit SRAM that operates at a 2.5V supply voltage. It features a fast access time of 10ns, making it an excellent choice for systems that require rapid data retrieval. Its asynchronous interface simplifies integration into a wide range of devices. In terms of power efficiency, the CY7C1318BV18 has a low operating current, ensuring that it can be utilized in battery-powered applications without significantly draining power.

Similarly, the CY7C1320BV18 offers a larger 256 Kbit capacity while maintaining the same low-voltage operation and performance characteristics. This chip also features a synchronous interface, supporting high-speed data transfer rates that are ideal for networking and communication devices. The CY7C1320BV18's features include deep-write operation capabilities, enhancing its performance in write-intensive applications.

The CY7C1916BV18 takes performance a step further with its 32 Megabit capacity, suitable for applications requiring extensive memory resources. This device also supports advanced functions such as burst read modes, allowing for faster sequential data access. With its low-latency performance, the CY7C1916BV18 is an excellent choice for applications like digital signal processing and real-time data analysis.

Lastly, the CY7C1316BV18 is another variant offering 1 Megabit of storage. It combines high-speed functionality with low power usage, supporting a wide range of applications including consumer electronics and automotive systems. Its robust design ensures reliability under varying environmental conditions.

All of these SRAM devices incorporate Cypress’s advanced semiconductor technology, providing a combination of speed, efficiency, and reliability. They are available in various package options, which facilitate easy integration into diverse system designs. Overall, the Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 exemplify the company’s commitment to delivering high-quality memory solutions that cater to the evolving needs of the electronic industry.
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