Cypress CY7C1316BV18, CY7C1318BV18, CY7C1320BV18, CY7C1916BV18 manual Syt, Nxr

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CY7C1316BV18, CY7C1916BV18

CY7C1318BV18, CY7C1320BV18

Document History Page

Document Title: CY7C1316BV18/CY7C1916BV18/CY7C1318BV18/CY7C1320BV18, 18-Mbit DDR-II SRAM 2-Word Burst Ar- chitecture

Document Number: 38-05621

Rev.

ECN No.

Submission

Orig, of

Description of Change

 

 

Date

Change

 

**

252474

See ECN

SYT

New data sheet

 

 

 

 

 

*A

325581

See ECN

SYT

Removed CY7C1320BV18 from the title

 

 

 

 

Included 300-MHz Speed Bin

 

 

 

 

Added Industrial Temperature Grade

 

 

 

 

Replaced TBDs for IDD and ISB1 specs

 

 

 

 

Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 28.51°C/W and

 

 

 

 

ΘJC = 5.91°C/W

 

 

 

 

Replaced TBDs in the Capacitance Table for the 165 FBGA Package

 

 

 

 

Changed the package diagram from BB165E (15 x 17 x 1.4 mm) to BB165D

 

 

 

 

(13 x 15 x 1.4 mm)

 

 

 

 

Added Lead-Free Product Information

 

 

 

 

Updated the Ordering Information by Shading and Unshading MPNs as per avail-

 

 

 

 

ability

*B

413997

See ECN

NXR

Converted from Preliminary to Final

 

 

 

 

Added CY7C1916BV18 part number to the title

 

 

 

 

Added 278-MHz speed Bin

 

 

 

 

Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901

 

 

 

 

North First Street” to “198 Champion Court”

 

 

 

 

Changed C/C Pin Description in the features section and Pin Description

 

 

 

 

Added power-up sequence details and waveforms

 

 

 

 

Added foot notes #15, 16, 17 on page# 19

 

 

 

 

Replaced Three-state with Tri-state

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage Current on

 

 

 

 

page# 20

 

 

 

 

Modified the IDD and ISB values

 

 

 

 

Modified test condition in Footnote #18 on page# 20 from VDDQ < VDD to

 

 

 

 

VDDQ < VDD

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

 

 

 

 

Updated Ordering Information Table

*C

472384

See ECN

NXR

Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD

 

 

 

 

to Alternately, this pin can be connected directly to VDDQ

 

 

 

 

Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD

 

 

 

 

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH

 

 

 

 

from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

 

 

 

 

Characteristics table

 

 

 

 

Modified Power-Up waveform

 

 

 

 

Changed the Maximum rating of Ambient Temperature with Power Applied from

 

 

 

 

–10°C to +85°C to –55°C to +125°C

 

 

 

 

Added additional notes in the AC parameter section

 

 

 

 

Modified AC Switching Waveform

 

 

 

 

Corrected the typo In the AC Switching Characteristics Table

 

 

 

 

Updated the Ordering Information Table

Document Number: 38-05621 Rev. *D

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Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1316BV18Logic Block Diagram CY7C1916BV18 CLKLogic Block Diagram CY7C1318BV18 Logic Block Diagram CY7C1320BV18BWS CY7C1316BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1916BV18 2M xCY7C1318BV18 1M x CY7C1320BV18 512K xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance SRAM#1 ZQFirst Address External Second Address Internal Write Cycle DescriptionsOperation CommentsDevice Write cycle description table for CY7C1916BV18 followsWrite cycle description table for CY7C1320BV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Input High Voltage Vref +Input LOW Voltage Vref Document Number 38-05621 Rev. *D Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms DON’T Care UndefinedOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSYT NXRVKN/PYRS Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions USB

CY7C1316BV18, CY7C1916BV18, CY7C1320BV18, CY7C1318BV18 specifications

The Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 are advanced synchronous static RAM (SRAM) devices designed to meet the high-performance requirements of modern computing systems. Offering a blend of high speed, low power consumption, and large storage capacities, these chips are widely utilized in applications such as networking equipment, telecommunications, and high-speed data processing.

The CY7C1318BV18 is a 2 Megabit SRAM that operates at a 2.5V supply voltage. It features a fast access time of 10ns, making it an excellent choice for systems that require rapid data retrieval. Its asynchronous interface simplifies integration into a wide range of devices. In terms of power efficiency, the CY7C1318BV18 has a low operating current, ensuring that it can be utilized in battery-powered applications without significantly draining power.

Similarly, the CY7C1320BV18 offers a larger 256 Kbit capacity while maintaining the same low-voltage operation and performance characteristics. This chip also features a synchronous interface, supporting high-speed data transfer rates that are ideal for networking and communication devices. The CY7C1320BV18's features include deep-write operation capabilities, enhancing its performance in write-intensive applications.

The CY7C1916BV18 takes performance a step further with its 32 Megabit capacity, suitable for applications requiring extensive memory resources. This device also supports advanced functions such as burst read modes, allowing for faster sequential data access. With its low-latency performance, the CY7C1916BV18 is an excellent choice for applications like digital signal processing and real-time data analysis.

Lastly, the CY7C1316BV18 is another variant offering 1 Megabit of storage. It combines high-speed functionality with low power usage, supporting a wide range of applications including consumer electronics and automotive systems. Its robust design ensures reliability under varying environmental conditions.

All of these SRAM devices incorporate Cypress’s advanced semiconductor technology, providing a combination of speed, efficiency, and reliability. They are available in various package options, which facilitate easy integration into diverse system designs. Overall, the Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 exemplify the company’s commitment to delivering high-quality memory solutions that cater to the evolving needs of the electronic industry.
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