Cypress CY7C1316BV18, CY7C1318BV18, CY7C1320BV18 Write Cycle Descriptions, Operation, Comments

Page 10

CY7C1316BV18, CY7C1916BV18

CY7C1318BV18, CY7C1320BV18

Truth Table

The truth table for the CY7C1316BV18, CY7C1916BV18, CY7C1318BV18, and CY7C1320BV18 follows. [2, 3, 4, 5, 6, 7]

Operation

K

LD

R/W

DQ

DQ

Write Cycle:

L-H

L

L

D(A1) at K(t + 1)

D(A2) at

 

 

K(t + 1)

Load address; wait one cycle;

 

 

 

 

 

 

 

 

 

input write data on consecutive K and

K

rising edges.

 

 

 

 

 

 

 

 

 

Read Cycle:

L-H

L

H

Q(A1) at

 

 

Q(A2) at C(t + 2)

C(t + 1)

Load address; wait one and a half cycle;

 

 

 

 

 

 

 

 

 

read data on consecutive C and C rising edges.

 

 

 

 

 

 

 

 

 

NOP: No Operation

L-H

H

X

High-Z

High-Z

Standby: Clock Stopped

Stopped

X

X

Previous State

Previous State

Burst Address Table

(CY7C1318BV18, CY7C1320BV18)

First Address (External)

Second Address (Internal)

X..X0

X..X1

 

 

X..X1

X..X0

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1316BV18 and CY7C1318BV18 follows. [2, 8]

 

BWS0/

BWS1/

K

 

 

 

Comments

 

 

 

 

K

 

 

 

 

 

 

 

 

 

 

 

 

NWS0

 

NWS1

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1316BV18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18 both bytes (D[17:0]) are written into the device.

 

 

 

L

 

L

L-H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1316BV18 both nibbles (D[7:0]) are written into the device.

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18 both bytes (D[17:0]) are written into the device.

 

 

 

L

 

H

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1316BV18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

L

 

H

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1316BV18 only the lower nibble (D[3:0]) is written into the device, D[7:4]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18 only the lower byte (D[8:0]) is written into the device, D[17:9]

remains unaltered.

 

H

 

L

L–H

 

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1316BV18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

L

L–H

During the data portion of a write sequence:

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1316BV18 only the upper nibble (D[7:4]) is written into the device, D[3:0]

remains unaltered.

 

 

 

 

 

 

 

 

 

 

CY7C1318BV18 only the upper byte (D[17:9]) is written into the device, D[8:0]

remains unaltered.

 

H

 

H

L–H

 

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

L–H

No data is written into the devices during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes

2.X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.

3.Device powers up deselected with the outputs in a tri-state condition.

4.On CY7C1318BV18 and CY7C1320BV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses sequence in the burst. On CY7C1316BV18 and CY7C1916BV18, “A1” represents A + ‘0’ and “A2” represents A + ‘1’.

5.“t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

6.Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7.It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

8.Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved.

Document Number: 38-05621 Rev. *D

Page 10 of 31

[+] Feedback

Image 10
Contents Functional Description FeaturesConfigurations Selection GuideDoff Logic Block Diagram CY7C1316BV18Logic Block Diagram CY7C1916BV18 CLKLogic Block Diagram CY7C1320BV18 Logic Block Diagram CY7C1318BV18BWS CY7C1316BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1916BV18 2M xCY7C1318BV18 1M x CY7C1320BV18 512K xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Referenced with Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Echo Clocks Application ExampleProgrammable Impedance SRAM#1 ZQFirst Address External Second Address Internal Write Cycle DescriptionsOperation CommentsDevice Write cycle description table for CY7C1916BV18 followsWrite cycle description table for CY7C1320BV18 follows Into the device. D359 remains unalteredIeee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBoundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Input High Voltage Vref + AC Electrical CharacteristicsInput LOW Voltage Vref Document Number 38-05621 Rev. *D Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitParameter Min Max Parameter Min Max Output Times DLL TimingSwitching Waveforms DON’T Care UndefinedOrdering Information 250 167 Package Diagram Ball Fbga 13 x 15 x 1.4 mmSYT NXRVKN/PYRS Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions USB

CY7C1316BV18, CY7C1916BV18, CY7C1320BV18, CY7C1318BV18 specifications

The Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 are advanced synchronous static RAM (SRAM) devices designed to meet the high-performance requirements of modern computing systems. Offering a blend of high speed, low power consumption, and large storage capacities, these chips are widely utilized in applications such as networking equipment, telecommunications, and high-speed data processing.

The CY7C1318BV18 is a 2 Megabit SRAM that operates at a 2.5V supply voltage. It features a fast access time of 10ns, making it an excellent choice for systems that require rapid data retrieval. Its asynchronous interface simplifies integration into a wide range of devices. In terms of power efficiency, the CY7C1318BV18 has a low operating current, ensuring that it can be utilized in battery-powered applications without significantly draining power.

Similarly, the CY7C1320BV18 offers a larger 256 Kbit capacity while maintaining the same low-voltage operation and performance characteristics. This chip also features a synchronous interface, supporting high-speed data transfer rates that are ideal for networking and communication devices. The CY7C1320BV18's features include deep-write operation capabilities, enhancing its performance in write-intensive applications.

The CY7C1916BV18 takes performance a step further with its 32 Megabit capacity, suitable for applications requiring extensive memory resources. This device also supports advanced functions such as burst read modes, allowing for faster sequential data access. With its low-latency performance, the CY7C1916BV18 is an excellent choice for applications like digital signal processing and real-time data analysis.

Lastly, the CY7C1316BV18 is another variant offering 1 Megabit of storage. It combines high-speed functionality with low power usage, supporting a wide range of applications including consumer electronics and automotive systems. Its robust design ensures reliability under varying environmental conditions.

All of these SRAM devices incorporate Cypress’s advanced semiconductor technology, providing a combination of speed, efficiency, and reliability. They are available in various package options, which facilitate easy integration into diverse system designs. Overall, the Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 exemplify the company’s commitment to delivering high-quality memory solutions that cater to the evolving needs of the electronic industry.