Cypress CY7C1318BV18 manual Write cycle description table for CY7C1916BV18 follows, Device

Page 11

CY7C1316BV18, CY7C1916BV18

CY7C1318BV18, CY7C1320BV18

Write Cycle Descriptions

The write cycle description table for CY7C1916BV18 follows. [2, 8]

BWS0

K

K

Comments

L

L–H

–

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

–

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

–

No data is written into the device during this portion of a write operation.

 

 

 

 

H

–

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1320BV18 follows. [2, 8]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

–

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

L

 

L

 

L

 

L

–

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

L

 

H

 

H

 

H

L–H

 

–

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

–

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

–

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

L

 

H

 

H

–

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remains unaltered.

 

H

 

H

 

L

 

H

L–H

 

–

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

L

 

H

–

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remains unaltered.

 

H

 

H

 

H

 

L

L–H

 

–

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

–

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

–

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

–

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 38-05621 Rev. *D

Page 11 of 31

[+] Feedback

Page 10 Page 12
Image 11
Page 10 Page 12
Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1316BV18Logic Block Diagram CY7C1916BV18 DoffBWS Logic Block Diagram CY7C1318BV18Logic Block Diagram CY7C1320BV18 CY7C1916BV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1316BV18 2M xCY7C1320BV18 512K x CY7C1318BV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Referenced with Respect toFunctional Overview SRAM#1 ZQ Application ExampleProgrammable Impedance Echo ClocksComments Write Cycle DescriptionsOperation First Address External Second Address InternalInto the device. D359 remains unaltered Write cycle description table for CY7C1916BV18 followsWrite cycle description table for CY7C1320BV18 follows DeviceIeee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics Input LOW Voltage Vref Document Number 38-05621 Rev. *D AC Electrical CharacteristicsInput High Voltage Vref + Parameter Description Test Conditions Fbga Unit CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitParameter Min Max DLL Timing Parameter Min Max Output TimesDON’T Care Undefined Switching WaveformsOrdering Information 250 167 Ball Fbga 13 x 15 x 1.4 mm Package DiagramNXR SYTUSB Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions VKN/PYRS

CY7C1316BV18, CY7C1916BV18, CY7C1320BV18, CY7C1318BV18 specifications

The Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 are advanced synchronous static RAM (SRAM) devices designed to meet the high-performance requirements of modern computing systems. Offering a blend of high speed, low power consumption, and large storage capacities, these chips are widely utilized in applications such as networking equipment, telecommunications, and high-speed data processing.

The CY7C1318BV18 is a 2 Megabit SRAM that operates at a 2.5V supply voltage. It features a fast access time of 10ns, making it an excellent choice for systems that require rapid data retrieval. Its asynchronous interface simplifies integration into a wide range of devices. In terms of power efficiency, the CY7C1318BV18 has a low operating current, ensuring that it can be utilized in battery-powered applications without significantly draining power.

Similarly, the CY7C1320BV18 offers a larger 256 Kbit capacity while maintaining the same low-voltage operation and performance characteristics. This chip also features a synchronous interface, supporting high-speed data transfer rates that are ideal for networking and communication devices. The CY7C1320BV18's features include deep-write operation capabilities, enhancing its performance in write-intensive applications.

The CY7C1916BV18 takes performance a step further with its 32 Megabit capacity, suitable for applications requiring extensive memory resources. This device also supports advanced functions such as burst read modes, allowing for faster sequential data access. With its low-latency performance, the CY7C1916BV18 is an excellent choice for applications like digital signal processing and real-time data analysis.

Lastly, the CY7C1316BV18 is another variant offering 1 Megabit of storage. It combines high-speed functionality with low power usage, supporting a wide range of applications including consumer electronics and automotive systems. Its robust design ensures reliability under varying environmental conditions.

All of these SRAM devices incorporate Cypress’s advanced semiconductor technology, providing a combination of speed, efficiency, and reliability. They are available in various package options, which facilitate easy integration into diverse system designs. Overall, the Cypress CY7C1318BV18, CY7C1320BV18, CY7C1916BV18, and CY7C1316BV18 exemplify the company’s commitment to delivering high-quality memory solutions that cater to the evolving needs of the electronic industry.
Top Page Image Contents