Cypress CY7C1307BV25, CY7C1305BV25 manual Introduction

			CY7C1305BV25
			CY7C1307BV25
Pin Definitions (continued)
Name		I/O	Description
NC/36M		N/A	Address expansion for 36M. This is not connected to the die. Can be connected to any
			voltage level on CY7C1305BV25/CY7C1307BV25.
GND/72M		Input	Address expansion for 72M. This should be tied LOW on the CY7C1305BV25.
NC/72M		N/A	Address expansion for 72M. This can be connected to any voltage level on
			CY7C1307BV25.
GND/144M		Input	Address expansion for 144M. This should be tied LOW on
			CY7C1305BV25/CY7C1307BV25.
GND/288M		Input	Address expansion for 144M. This should be tied LOW on CY7C1307BV25.
VREF		Input-	Reference Voltage Input. Static input used to set the reference level for HSTL inputs
	Reference		and Outputs as well as AC measurement points.
VDD	Power Supply		Power supply inputs to the core of the device
VSS		Ground	Ground for the device
VDDQ	Power Supply		Power supply inputs for the outputs of the device
NC		N/A	Not connected to the die. Can be tied to any voltage level.

Introduction

Functional Overview

The CY7C1305BV25/CY7C1307BV25 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the device completely elimi- nates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 18-bit data transfers in the case of CY7C1305BV25 and four 36-bit data transfers in the case of CY7C1307BV25, in two clock cycles.

Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is refer- enced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of output clocks (C and C, or K and K when in single clock mode).

All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS[0:x]) inputs pass through input registers controlled by the rising edge of input clocks (K and K).

CY7C1305BV25 is described in the following sections. The same basic descriptions apply to CY7C1307BV25.

Read Operations

The CY7C1305BV25 is organized internally as 4 arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the

Document #: 38-05630 Rev. *A

subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode, 250-MHz device). In order to maintain the internal logic, each Read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode).

When the read port is deselected, the CY7C1305BV25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the positive clock (K). Doing so will pipeline the data flow such that 18-bits of data can be trans- ferred into the device on every rising edge of the input clocks (K and K).

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