Cypress CY7C1305BV25, CY7C1307BV25 manual Pin Definitions

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CY7C1305BV25

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1307BV25

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Name

 

I/O

 

 

 

Description

 

 

D[x:0]

 

Input-

Data input signals, sampled on the rising edge of K and

K

clocks during valid write

 

 

 

 

 

 

 

 

 

 

Synchronous

operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1305BV25 – D[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1307BV25 – D[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Write Port Select, active LOW. Sampled on the rising edge of the K clock. When

 

 

WPS

 

 

 

 

 

 

 

 

 

 

 

Synchronous

asserted active, a Write operation is initiated. Deasserting will deselect the Write port.

 

 

 

 

 

 

 

 

 

 

 

 

 

Deselecting the Write port will cause D[x:0] to be ignored.

 

 

 

 

 

 

0,

 

 

1,

 

Input-

Byte Write Select 0, 1, 2, and 3–active LOW. Sampled on the rising edge of the K and

 

 

BWS

BWS

 

 

 

BWS2, BWS3

Synchronous

K clocks during Write operations. Used to select which byte is written into the device

 

 

 

 

 

 

 

 

 

 

 

 

 

during the current portion of the Write operations. Bytes not written remain unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1305BV25 - BWS0

controls D[8:0] and BWS1 controls D[17:9].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1307BV25 - BWS0

controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18]

 

 

 

 

 

 

 

 

 

 

 

 

 

and BWS3 controls D[35:27]

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a

 

 

 

 

 

 

 

 

 

 

 

 

 

Byte Write Select will cause the corresponding byte of data to be ignored and not written

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device.

 

 

 

 

 

 

 

 

 

 

 

 

A

 

Input-

Address Inputs. Sampled on the rising edge of the K clock during active Read and Write

 

 

 

 

 

 

 

 

 

 

Synchronous

operations. These address inputs are multiplexed for both Read and Write operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1305BV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307BV25.

 

 

 

 

 

 

 

 

 

 

 

 

 

Therefore, only 18 address inputs for CY7C1305BV25 and 17 address inputs for

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1307BV25. These inputs are ignored when the appropriate port is deselected.

 

 

Q[x:0]

Outputs-

Data Output signals. These pins drive out the requested data during a Read operation.

 

 

 

 

 

 

 

 

 

 

Synchronous

Valid data is driven out on the rising edge of both the C and C clocks during Read

 

 

 

 

 

 

 

 

 

 

 

 

 

operations or K and K when in single clock mode. When the Read port is deselected,

 

 

 

 

 

 

 

 

 

 

 

 

 

Q[x:0] are automatically three-stated.

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1305BV25 - Q[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1307BV25 - Q[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K).

 

 

RPS

 

 

 

 

 

 

 

 

 

 

 

Synchronous

When active, a Read operation is initiated. Deasserting will cause the Read port to be

 

 

 

 

 

 

 

 

 

 

 

 

 

deselected. When deselected, the pending access is allowed to complete and the output

 

 

 

 

 

 

 

 

 

 

 

 

 

drivers are automatically three-stated following the next rising edge of the C clock. Each

 

 

 

 

 

 

 

 

 

 

 

 

 

read access consists of a burst of four sequential 18-bit or 36-bit transfers.

 

 

C

Input-Clock

Positive Input Clock for Output Data. C is used in conjunction with

 

to clock out the

 

 

C

 

 

 

 

 

 

 

 

 

 

 

 

 

Read data from the device. C and C can be used together to deskew the flight times of

 

 

 

 

 

 

 

 

 

 

 

 

 

various devices on the board back to the controller. See application example for further

 

 

 

 

 

 

 

 

 

 

 

 

 

details.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-Clock

Negative Input Clock for Output Data.

 

is used in conjunction with C to clock out the

 

 

C

C

 

 

 

 

 

 

 

 

 

 

 

 

 

Read data from the device. C and C can be used together to deskew the flight times of

 

 

 

 

 

 

 

 

 

 

 

 

 

various devices on the board cack to the controller. See application example for further

 

 

 

 

 

 

 

 

 

 

 

 

 

details.

 

 

 

 

 

 

 

 

 

 

 

 

K

Input-Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs

 

 

 

 

 

 

 

 

 

 

 

 

 

to the device and to drive out data through Q[x:0] when in single clock mode. All accesses

 

 

 

 

 

 

 

 

 

 

 

 

 

are initiated on the rising edge of K.

 

 

 

 

Input-Clock

Negative Input Clock Input.

 

is used to capture synchronous inputs to the device and

 

 

K

K

 

 

 

 

 

 

 

 

 

 

 

 

 

to drive out data through Q[x:0] when in single clock mode.

 

 

ZQ

 

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the

 

 

 

 

 

 

 

 

 

 

 

 

 

system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is

 

 

 

 

 

 

 

 

 

 

 

 

 

a resistor connected between ZQ and ground. Alternately, this pin can be connected

 

 

 

 

 

 

 

 

 

 

 

 

 

directly to VDDQ, which enables the minimum impedance mode. This pin cannot be

 

 

 

 

 

 

 

 

 

 

 

 

 

connected directly to VSS or left unconnected.

 

 

TDO

 

Output

TDO pin for JTAG

 

 

 

 

 

 

 

 

 

 

 

 

TCK

 

Input

TCK pin for JTAG

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

Input

TDI pin for JTAG

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

Input

TMS pin for JTAG

 

 

 

 

 

 

 

 

 

 

Document #: 38-05630 Rev. *A

 

 

 

 

 

 

 

 

 

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Contents Features ConfigurationsFunctional Description CY7C1305BV25 1M x CY7C1307BV25 512K xLogic Block Diagram CY7C1305BV25 Logic Block Diagram CY7C1307BV25Selection Guide CY7C1305BV25-167 UnitPin\Configuration Ball Fbga 13 x 15 x 1.4 mm Pinout CY7C1307BV25 512K xPin Definitions Introduction Application Example1 Write Cycle Descriptions CY7C1305BV25 2 OperationWrite Cycle Read CycleWrite Cycle Descriptions CY7C1307BV25 2 Are written into the deviceOperation Operation Document # 38-05630 Rev. *AIeee 1149.1 Serial Boundary Scan Jtag Sample Z TAP Controller State Diagram11 EXIT2-IR UPDATE-DR UPDATE-IRTAP Controller Block Diagram Parameter Description Test Conditions Min Max UnitParameter Description Min Max Unit Set-up TimesTAP Timing and Test Conditions14 Identification Register DefinitionsParameter Description Min Max Unit Output Times TCK Clock LOW to TDO ValidScan Register Sizes Instruction CodesRegister Name Bit Size Instruction Code DescriptionBoundary Scan Order Bit # Bump IDOperating Range Maximum RatingsThermal Resistance22 Capacitance22 AC Test Loads and WaveformsParameter Description Test Conditions Max Unit Input Capacitance TA = 25C, f = 1 MHz VDD =Switching Characteristics Over the Operating Range23 Cycle TimeSwitching Waveforms27, 28 NOP Read WritePackage Diagram Ordering InformationCY7C1307BV25-167BZC CY7C1305BV25-167BZXC CY7C1307BV25-167BZI CY7C1305BV25-167BZXIIssue Date Orig. Description of Change Document HistorySYT NXR

CY7C1307BV25, CY7C1305BV25 specifications

Cypress Semiconductor, a leader in embedded memory solutions, includes the CY7C1305BV25 and CY7C1307BV25 in its family of high-performance synchronous dynamic random-access memory (SDRAM) devices. These memory chips are designed for applications that require high-speed data processing and low power consumption, making them ideal for communication systems, networking devices, and other consumer electronics.

The CY7C1305BV25 is a 512K x 16-bit synchronous SRAM, while the CY7C1307BV25 offers a larger capacity of 1M x 16-bit. Both chips operate at a maximum clock frequency of 166 MHz, ensuring rapid data transfer rates and efficient memory operation. This high-speed performance is crucial in applications where quick data retrieval and storage are imperative.

One of the standout features of these devices is their ability to support a wide range of operating voltages, typically from 2.5V to 3.3V. This versatility allows them to be integrated into systems with varying power requirements, enhancing their adaptability for different designs. Additionally, the chips offer a low standby power consumption level, contributing to energy efficiency in battery-operated devices.

Both the CY7C1305BV25 and CY7C1307BV25 utilize a synchronous interface, allowing for coordinated data transfer with the system clock. This synchronization minimizes latency and improves overall system performance. The use of advanced pipelining techniques enables these devices to process multiple read and write commands concurrently, further boosting throughput.

In terms of reliability and durability, Cypress ensures that these memory chips comply with stringent industry standards. They are designed to withstand a wide temperature range, making them suitable for operation in diverse environments. The robust design includes features that mitigate the risk of data corruption and enhance data integrity, which is a vital consideration in mission-critical applications.

Overall, the CY7C1305BV25 and CY7C1307BV25 represent Cypress Semiconductor's commitment to delivering high-quality, high-performance memory solutions that meet the demanding requirements of modern electronics. Their impressive features, combined with a focus on low power consumption and reliability, make them a preferred choice for engineers and developers aiming to create the next generation of innovative products.
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