Cypress CY7C1307BV25 Write Cycle Descriptions CY7C1305BV25 2, Operation, Read Cycle, Comments

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CY7C1305BV25

CY7C1307BV25

Truth Table[2, 3, 4, 5, 6, 7, 8, 9]

 

 

 

Operation

 

 

K

 

RPS

WPS

DQ

DQ

DQ

DQ

Write Cycle:

 

L-H

 

H[8]

L[9]

D(A+00) at

D(A+01) at

D(A+10) at

D(A+11) at

Load address on the rising

 

 

 

 

 

 

 

K(t+1) ↑

K(t+1) ↑

K(t+2) ↑

K(t+2) ↑

edge of K; wait one cycle;

 

 

 

 

 

 

 

 

 

 

 

input write data on two

 

 

 

 

 

 

 

 

 

 

 

consecutive K and K rising

 

 

 

 

 

 

 

 

 

 

 

edges.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read Cycle:

 

L-H

 

L[9]

X

Q(A+00) at

Q(A+01) at

Q(A+10) at

Q(A+11) at

Load address on the rising

 

 

 

 

 

 

 

C(t+1) ↑

C(t+1) ↑

C(t+2) ↑

C(t+2) ↑

edge of K; wait one cycle;

 

 

 

 

 

 

 

 

 

 

 

read data on two consec-

 

 

 

 

 

 

 

 

 

 

 

utive C and

C

rising edges.

 

 

 

 

 

 

 

 

 

 

 

NOP: No operation

 

L-H

 

H

H

D = X

D = X

D = X

D = X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q = High-Z

Q = High-Z

Q = High-Z

Q = High-Z

Standby: Clock stopped

Stopped

 

X

X

Previous state

Previous state

Previous state

Previous state

Write Cycle Descriptions (CY7C1305BV25)[2, 10]

 

 

 

 

BWS

0

 

 

BWS

1

K

 

K

 

 

 

 

 

 

Comments

 

 

 

L

 

 

 

 

L

L-H

 

–

 

During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.

 

L

 

 

 

 

L

–

L-H

 

During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device.

 

L

 

 

 

H

L-H

 

–

 

During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

device. D[17:9] will remain unaltered.

 

 

 

L

 

 

 

H

–

L-H

 

During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

device. D[17:9] will remain unaltered.

 

 

 

H

 

 

 

 

L

L-H

 

–

 

During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] will remain unaltered.

 

 

 

H

 

 

 

 

L

–

L-H

 

During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] will remain unaltered.

 

 

 

H

 

 

 

H

L-H

 

–

 

No data is written into the device during this portion of a Write operation.

 

H

 

 

 

H

–

L-H

 

No data is written into the device during this portion of a Write operation.

Notes:

2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

3. Device will power-up deselected and the outputs in a three-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read request.

10.Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 in the case of CY7C1305BV25 and BWS2 and BWS3 in the case of CY7C1307BV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.

Document #: 38-05630 Rev. *A

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Contents CY7C1305BV25 1M x CY7C1307BV25 512K x FeaturesConfigurations Functional DescriptionCY7C1305BV25-167 Unit Logic Block Diagram CY7C1305BV25Logic Block Diagram CY7C1307BV25 Selection GuideCY7C1307BV25 512K x Pin\Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutPin Definitions Introduction Application Example1 Read Cycle Write Cycle Descriptions CY7C1305BV25 2Operation Write CycleOperation Document # 38-05630 Rev. *A Write Cycle Descriptions CY7C1307BV25 2Are written into the device OperationIeee 1149.1 Serial Boundary Scan Jtag Sample Z EXIT2-IR UPDATE-DR UPDATE-IR TAP Controller State Diagram11Set-up Times TAP Controller Block DiagramParameter Description Test Conditions Min Max Unit Parameter Description Min Max UnitTCK Clock LOW to TDO Valid TAP Timing and Test Conditions14Identification Register Definitions Parameter Description Min Max Unit Output TimesInstruction Code Description Scan Register SizesInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderOperating Range Maximum RatingsThermal Resistance22 Input Capacitance TA = 25C, f = 1 MHz VDD = Capacitance22AC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCycle Time Switching Characteristics Over the Operating Range23NOP Read Write Switching Waveforms27, 28CY7C1307BV25-167BZI CY7C1305BV25-167BZXI Package DiagramOrdering Information CY7C1307BV25-167BZC CY7C1305BV25-167BZXCNXR Issue Date Orig. Description of ChangeDocument History SYT

CY7C1307BV25, CY7C1305BV25 specifications

Cypress Semiconductor, a leader in embedded memory solutions, includes the CY7C1305BV25 and CY7C1307BV25 in its family of high-performance synchronous dynamic random-access memory (SDRAM) devices. These memory chips are designed for applications that require high-speed data processing and low power consumption, making them ideal for communication systems, networking devices, and other consumer electronics.

The CY7C1305BV25 is a 512K x 16-bit synchronous SRAM, while the CY7C1307BV25 offers a larger capacity of 1M x 16-bit. Both chips operate at a maximum clock frequency of 166 MHz, ensuring rapid data transfer rates and efficient memory operation. This high-speed performance is crucial in applications where quick data retrieval and storage are imperative.

One of the standout features of these devices is their ability to support a wide range of operating voltages, typically from 2.5V to 3.3V. This versatility allows them to be integrated into systems with varying power requirements, enhancing their adaptability for different designs. Additionally, the chips offer a low standby power consumption level, contributing to energy efficiency in battery-operated devices.

Both the CY7C1305BV25 and CY7C1307BV25 utilize a synchronous interface, allowing for coordinated data transfer with the system clock. This synchronization minimizes latency and improves overall system performance. The use of advanced pipelining techniques enables these devices to process multiple read and write commands concurrently, further boosting throughput.

In terms of reliability and durability, Cypress ensures that these memory chips comply with stringent industry standards. They are designed to withstand a wide temperature range, making them suitable for operation in diverse environments. The robust design includes features that mitigate the risk of data corruption and enhance data integrity, which is a vital consideration in mission-critical applications.

Overall, the CY7C1305BV25 and CY7C1307BV25 represent Cypress Semiconductor's commitment to delivering high-quality, high-performance memory solutions that meet the demanding requirements of modern electronics. Their impressive features, combined with a focus on low power consumption and reliability, make them a preferred choice for engineers and developers aiming to create the next generation of innovative products.
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