Cypress CY7C1305BV25, CY7C1307BV25 manual Application Example1

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CY7C1305BV25

CY7C1307BV25

When deselected, the write port will ignore all inputs after the pending Write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1305BV25. A write operation is initiated as described in the Write Operation section above. The bytes that are written are deter- mined by BWS0 and BWS1, which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation.

Single Clock Mode

The CY7C1305BV25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and

K)that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation.

Concurrent Transactions

The Read and Write ports on the CY7C1305BV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the trans- action on the other port. If the ports access the same location at the same time, the SRAM will deliver the most recent infor- mation associated with the specified address location. This

includes forwarding data from a Write cycle that was initiated on the previous K clock rise.

Read and Write accesses must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read.

Depth Expansion

The CY7C1305BV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ=1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature.

Application Example[1]

Note:

1. The above application shows four QDR-I being used.

Document #: 38-05630 Rev. *A

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Contents Functional Description FeaturesConfigurations CY7C1305BV25 1M x CY7C1307BV25 512K xSelection Guide Logic Block Diagram CY7C1305BV25Logic Block Diagram CY7C1307BV25 CY7C1305BV25-167 UnitPin\Configuration Ball Fbga 13 x 15 x 1.4 mm Pinout CY7C1307BV25 512K xPin Definitions Introduction Application Example1 Write Cycle Write Cycle Descriptions CY7C1305BV25 2Operation Read CycleOperation Write Cycle Descriptions CY7C1307BV25 2Are written into the device Operation Document # 38-05630 Rev. *AIeee 1149.1 Serial Boundary Scan Jtag Sample Z TAP Controller State Diagram11 EXIT2-IR UPDATE-DR UPDATE-IRParameter Description Min Max Unit TAP Controller Block DiagramParameter Description Test Conditions Min Max Unit Set-up TimesParameter Description Min Max Unit Output Times TAP Timing and Test Conditions14Identification Register Definitions TCK Clock LOW to TDO ValidRegister Name Bit Size Scan Register SizesInstruction Codes Instruction Code DescriptionBoundary Scan Order Bit # Bump IDMaximum Ratings Operating RangeThermal Resistance22 Parameter Description Test Conditions Max Unit Capacitance22AC Test Loads and Waveforms Input Capacitance TA = 25C, f = 1 MHz VDD =Switching Characteristics Over the Operating Range23 Cycle TimeSwitching Waveforms27, 28 NOP Read WriteCY7C1307BV25-167BZC CY7C1305BV25-167BZXC Package DiagramOrdering Information CY7C1307BV25-167BZI CY7C1305BV25-167BZXISYT Issue Date Orig. Description of ChangeDocument History NXR

CY7C1307BV25, CY7C1305BV25 specifications

Cypress Semiconductor, a leader in embedded memory solutions, includes the CY7C1305BV25 and CY7C1307BV25 in its family of high-performance synchronous dynamic random-access memory (SDRAM) devices. These memory chips are designed for applications that require high-speed data processing and low power consumption, making them ideal for communication systems, networking devices, and other consumer electronics.

The CY7C1305BV25 is a 512K x 16-bit synchronous SRAM, while the CY7C1307BV25 offers a larger capacity of 1M x 16-bit. Both chips operate at a maximum clock frequency of 166 MHz, ensuring rapid data transfer rates and efficient memory operation. This high-speed performance is crucial in applications where quick data retrieval and storage are imperative.

One of the standout features of these devices is their ability to support a wide range of operating voltages, typically from 2.5V to 3.3V. This versatility allows them to be integrated into systems with varying power requirements, enhancing their adaptability for different designs. Additionally, the chips offer a low standby power consumption level, contributing to energy efficiency in battery-operated devices.

Both the CY7C1305BV25 and CY7C1307BV25 utilize a synchronous interface, allowing for coordinated data transfer with the system clock. This synchronization minimizes latency and improves overall system performance. The use of advanced pipelining techniques enables these devices to process multiple read and write commands concurrently, further boosting throughput.

In terms of reliability and durability, Cypress ensures that these memory chips comply with stringent industry standards. They are designed to withstand a wide temperature range, making them suitable for operation in diverse environments. The robust design includes features that mitigate the risk of data corruption and enhance data integrity, which is a vital consideration in mission-critical applications.

Overall, the CY7C1305BV25 and CY7C1307BV25 represent Cypress Semiconductor's commitment to delivering high-quality, high-performance memory solutions that meet the demanding requirements of modern electronics. Their impressive features, combined with a focus on low power consumption and reliability, make them a preferred choice for engineers and developers aiming to create the next generation of innovative products.
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