Cypress CY7C1320JV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Page 17

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Identification Register Definitions

Instruction Field

 

Value

 

Description

CY7C1316JV18

CY7C1916JV18

CY7C1318JV18

CY7C1320JV18

 

 

Revision Number

001

001

001

001

Version number.

(31:29)

 

 

 

 

 

Cypress Device ID

11010100010000101

11010100010001101

11010100010010101

11010100010100101

Defines the type of

(28:12)

 

 

 

 

SRAM.

Cypress JEDEC ID

00000110100

00000110100

00000110100

00000110100

Allows unique

(11:1)

 

 

 

 

identification of

 

 

 

 

 

SRAM vendor.

ID Register

1

1

1

1

Indicates the

Presence (0)

 

 

 

 

presence of an ID

 

 

 

 

 

register.

Scan Register Sizes

Register Name

Bit Size

Instruction

3

 

 

Bypass

1

 

 

ID

32

 

 

Boundary Scan

107

 

 

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI

 

 

and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operation.

Document Number: 001-15271 Rev. *B

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1916JV18 Logic Block Diagram CY7C1316JV18Doff CLKBWS Logic Block Diagram CY7C1318JV18Logic Block Diagram CY7C1320JV18 Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1316JV18 2M x CY7C1916JV18 2M xCY7C1320JV18 512K x CY7C1318JV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSRAM#1 ZQ SRAM#2NWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence DC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitDLL Timing Cypress Consortium Description 300 MHz UnitParameter Min Max NOP Switching WaveformsRead NOP Write ReadOrdering Information Ball Fbga 13 x 15 x 1.40 mm Package DiagramVKN/AESA REV ECN no Issue ORIG. Description of Change DateVKN/KKVTMP