Cypress CY7C1320JV18 Pin Configuration, Ball Fbga 13 x 15 x 1.4 mm Pinout, CY7C1316JV18 2M x

Page 4

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Pin Configuration

The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow. [1]

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1316JV18 (2M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

CQ

R/W

NWS1

K

NC/144M

LD

A

NC/36M

CQ

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1916JV18 (2M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

NC/36M

CQ

CQ

R/W

K

LD

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

C

A

A

NC

NC

DQ8

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/36M, NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-15271 Rev. *B

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1316JV18 Logic Block Diagram CY7C1916JV18Doff CLKLogic Block Diagram CY7C1320JV18 Logic Block Diagram CY7C1318JV18BWS Pin Configuration Ball Fbga 13 x 15 x 1.4 mm PinoutCY7C1316JV18 2M x CY7C1916JV18 2M xCY7C1318JV18 1M x CY7C1320JV18 512K xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Application Example Echo ClocksSRAM#1 ZQ SRAM#2BWS0 BWS1 Write Cycle DescriptionsNWS0 NWS1 BWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints Electrical Characteristics DC Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsCapacitance Thermal ResistanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max Cypress Consortium Description 300 MHz UnitDLL Timing Switching Waveforms NOPRead NOP Write ReadOrdering Information Package Diagram Ball Fbga 13 x 15 x 1.40 mmVKN/KKVTMP REV ECN no Issue ORIG. Description of Change DateVKN/AESA