Cypress CY7C1916JV18 manual Switching Waveforms, Nop, NOP Write Read, DON’T Care Undefined

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CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Switching Waveforms

Figure 3. Read/Write/Deselect Sequence [24, 25, 26]

NOP		READ	READ
1		2	3
K
tKH	tKL	tCYC	tKHKH
K
LD	tSC
	tSC	tHC
R/W

NOP	NOP	WRITE	WRITE	READ
4	5	6	7	8	9	10

A	A0	A1
tSA		tHA

tKHCH tCLZ tCO

tHD

tSD

Q00 Q01 Q10	Q11
tCQDOH
tDOH	tCHZ
tCQD

tHD

tSD

D21

D30

D31

Q41

t KHCH

tKH tKL	tCYC	tKHKH

tCQOH

tCCQO

tCQOH

CQ#

tCCQO	tCQH	tCQHCQH

DON’T CARE

UNDEFINED

Notes

24.Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.

25.Outputs are disabled (High-Z) one clock cycle after a NOP.

26.In this example, if address A2 = A1, then data D20 = Q10 and D21 = Q11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

Document Number: 001-15271 Rev. *B

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Contents Selection Guide FeaturesConfigurations Functional DescriptionCLK Logic Block Diagram CY7C1316JV18Logic Block Diagram CY7C1916JV18 DoffBWS Logic Block Diagram CY7C1318JV18Logic Block Diagram CY7C1320JV18 CY7C1916JV18 2M x Pin ConfigurationBall Fbga 13 x 15 x 1.4 mm Pinout CY7C1316JV18 2M xCY7C1320JV18 512K x CY7C1318JV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description TDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device Is Referenced with Respect toFunctional Overview SRAM#2 Application ExampleEcho Clocks SRAM#1 ZQNWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical CharacteristicsParameter Description Test Conditions Max Unit CapacitanceThermal Resistance AC Test Loads and WaveformsDLL Timing Cypress Consortium Description 300 MHz UnitParameter Min Max NOP Write Read Switching WaveformsNOP ReadOrdering Information Ball Fbga 13 x 15 x 1.40 mm Package DiagramVKN/AESA REV ECN no Issue ORIG. Description of Change DateVKN/KKVTMP