Cypress CY7C1318JV18 Logic Block Diagram CY7C1316JV18, Logic Block Diagram CY7C1916JV18, Doff

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Logic Block Diagram (CY7C1316JV18)

20

A(19:0)

LD

K

K

DOFF

VREF

R/W

NWS[1:0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
Decode	Reg	Reg	Decode
	1M x	1M x			8
WriteAdd.	8Array	8Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

16							CQ
8		Reg.	Reg.	8			CQ
	8				8
				8		DQ[7:0]
		Reg.

Logic Block Diagram (CY7C1916JV18)

20

A(19:0)

LD

K

K

DOFF

VREF

R/W

BWS[0]

Address Register

CLK

Gen.

Control

Logic

	Write	Write
Decode	Reg	Reg	Decode
	1M x	1M x			9
WriteAdd.	9Array	9Array	ReadAdd.	Logic
				Output	R/W
	Read Data Reg.			Control	C
					C

18							CQ
9		Reg.	Reg.	9			CQ
	9				9
				9		DQ[8:0]
		Reg.

Document Number: 001-15271 Rev. *B Page 2 of 26

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