Cypress CY7C1316JV18, CY7C1916JV18 manual CY7C1318JV18 1M x, CY7C1320JV18 512K x

Page 5

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Pin Configuration

The pin configuration for CY7C1316JV18, CY7C1318JV18, and CY7C1320JV18 follow. [1] (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1318JV18 (1M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

CQ

R/W

BWS1

K

NC/144M

LD

A

NC/36M

CQ

B

NC

DQ9

NC

A

NC/288M

K

0

A

NC

NC

DQ8

BWS

C

NC

NC

NC

VSS

A

A0

A

VSS

NC

DQ7

NC

D

NC

NC

DQ10

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ11

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ6

F

NC

DQ12

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

NC

DQ13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ4

NC

K

NC

NC

DQ14

VDDQ

VDD

VSS

VDD

VDDQ

NC

D3

DQ3

L

NC

DQ15

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

DQ1

NC

N

NC

NC

DQ16

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ17

A

A

C

A

A

NC

NC

DQ0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1320JV18 (512K x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

NC/36M

CQ

R/W

BWS2

K

BWS1

LD

A

NC/72M

CQ

B

NC

DQ27

DQ18

A

3

K

0

A

NC

NC

DQ8

BWS

BWS

C

NC

NC

DQ28

VSS

A

A0

A

VSS

NC

DQ17

DQ7

D

NC

DQ29

DQ19

VSS

VSS

VSS

VSS

VSS

NC

NC

DQ16

E

NC

NC

DQ20

VDDQ

VSS

VSS

VSS

VDDQ

NC

DQ15

DQ6

F

NC

DQ30

DQ21

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

DQ31

DQ22

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ14

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

DQ32

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ13

DQ4

K

NC

NC

DQ23

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ12

DQ3

L

NC

DQ33

DQ24

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

DQ34

VSS

VSS

VSS

VSS

VSS

NC

DQ11

DQ1

N

NC

DQ35

DQ25

VSS

A

A

A

VSS

NC

NC

DQ10

P

NC

NC

DQ26

A

A

C

A

A

NC

DQ9

DQ0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Document Number: 001-15271 Rev. *B

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1916JV18 Logic Block Diagram CY7C1316JV18Doff CLKBWS Logic Block Diagram CY7C1318JV18Logic Block Diagram CY7C1320JV18 Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1316JV18 2M x CY7C1916JV18 2M xCY7C1320JV18 512K x CY7C1318JV18 1M xSynchronous Read/Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSRAM#1 ZQ SRAM#2NWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsInstruction Codes Identification Register DefinitionsScan Register Sizes Bit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence DC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitDLL Timing Cypress Consortium Description 300 MHz UnitParameter Min Max NOP Switching WaveformsRead NOP Write ReadOrdering Information Ball Fbga 13 x 15 x 1.40 mm Package DiagramVKN/AESA REV ECN no Issue ORIG. Description of Change DateVKN/KKVTMP