Cypress CY7C1320JV18, CY7C1316JV18, CY7C1318JV18 manual Package Diagram, Ball Fbga 13 x 15 x 1.40 mm

Page 25

CY7C1316JV18, CY7C1916JV18

CY7C1318JV18, CY7C1320JV18

Package Diagram

Figure 4. 165-ball FBGA (13 x 15 x 1.40 mm), 51-85180

15.00±0.10

A

TOP VIEW

PIN 1 CORNER

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1.00

15.00±0.10

14.00

 

7.00

A

BOTTOM VIEW

PIN 1 CORNER

Ø0.05 M C

Ø0.25 M C A B

-0.06

Ø0.50 (165X)

+0.14

11

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

1.00

5.00

10.00

0.25 C

 

B

0.53±0.05

 

0.36

C

 

13.00±0.10

 

 

1.40MAX.

 

 

 

 

 

 

 

 

 

0.15C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SEATING PLANE

0.35±0.06

B 13.00±0.10

0.15(4X)

NOTES :

SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)

PACKAGE WEIGHT : 0.475g

JEDEC REFERENCE : MO-216 / DESIGN 4.6C PACKAGE CODE : BB0AC

51-85180-*A

Document Number: 001-15271 Rev. *B

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1916JV18 Logic Block Diagram CY7C1316JV18Doff CLKLogic Block Diagram CY7C1320JV18 Logic Block Diagram CY7C1318JV18BWS Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1316JV18 2M x CY7C1916JV18 2M xCY7C1320JV18 512K x CY7C1318JV18 1M xPin Name Pin Description Pin DefinitionsSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSRAM#1 ZQ SRAM#2BWS0 BWS1 Write Cycle DescriptionsNWS0 NWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence Power Up Sequence in DDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitParameter Min Max Cypress Consortium Description 300 MHz UnitDLL Timing NOP Switching WaveformsRead NOP Write ReadOrdering Information Ball Fbga 13 x 15 x 1.40 mm Package DiagramVKN/KKVTMP REV ECN no Issue ORIG. Description of Change DateVKN/AESA
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