Cypress CY7C1320JV18, CY7C1316JV18 manual Application Example, Echo Clocks, SRAM#1 ZQ, SRAM#2

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CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18

driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles at power up to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the DDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchro- nized to the output clock of the DDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timing for the echo clocks is shown in Switching Characteristics on page 22.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30 ns. However, it is not necessary for the to specif- ically reset the DLL to lock it to the desired frequency. The DLL automatically locks 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with one cycle latency and a longer access time). For information refer to the application note DLL Considerations in QDRII™/DDRII.

Application Example

Figure 1 shows two DDR-II used in an application.

Figure 1. Application Example

SRAM#1 ZQ

DQCQ/CQ#

A LD# R/W# C C# K K#

 

DQ

 

BUS

Addresses

 

MASTER

Cycle Start#

 

(CPU

R/W#

 

or

Return CLK

Vterm = 0.75V

ASIC)

Source CLK

R = 50ohms

 

Return CLK#

 

Vterm = 0.75V

 

Source CLK#

 

 

Echo Clock1/Echo Clock#1

 

Echo Clock2/Echo Clock#2

 

R = 250ohms

SRAM#2

 

ZQ

 

 

 

 

 

DQ

CQ/CQ#

 

 

 

 

A LD# R/W# C C#

K K#

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R = 250ohms

Document Number: 001-15271 Rev. *B

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1916JV18 Logic Block Diagram CY7C1316JV18Doff CLKLogic Block Diagram CY7C1318JV18 Logic Block Diagram CY7C1320JV18BWS Ball Fbga 13 x 15 x 1.4 mm Pinout Pin ConfigurationCY7C1316JV18 2M x CY7C1916JV18 2M xCY7C1320JV18 512K x CY7C1318JV18 1M xPin Definitions Pin Name Pin DescriptionSynchronous Read/Write Input. When Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced with Respect to TDO for JtagFunctional Overview Echo Clocks Application ExampleSRAM#1 ZQ SRAM#2Write Cycle Descriptions BWS0 BWS1NWS0 NWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence in DDR-II Sram Power Up SequenceDLL Constraints DC Electrical Characteristics Electrical CharacteristicsAC Electrical Characteristics Maximum RatingsThermal Resistance CapacitanceAC Test Loads and Waveforms Parameter Description Test Conditions Max UnitCypress Consortium Description 300 MHz Unit Parameter Min MaxDLL Timing NOP Switching WaveformsRead NOP Write ReadOrdering Information Ball Fbga 13 x 15 x 1.40 mm Package DiagramREV ECN no Issue ORIG. Description of Change Date VKN/KKVTMPVKN/AESA
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