Cypress CY7C1916JV18, CY7C1316JV18, CY7C1320JV18 Power Up Sequence in DDR-II Sram, DLL Constraints

CY7C1316JV18, CY7C1916JV18 CY7C1318JV18, CY7C1320JV18

Power Up Sequence in DDR-II SRAM

DDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During power up, when the DOFF is tied HIGH, the DLL is locked after 1024 cycles of stable clock.

Power Up Sequence

■Apply power and drive DOFF LOW (all other inputs can be HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

■After the power and clock (K, K) are stable take DOFF HIGH

■The additional 1024 cycles of clocks are required for the DLL to lock.

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency.

Power Up Waveforms

K

K

VDD/ VDDQ

DOFF

~ ~

	~ ~
Unstable Clock	> 1024 Stable clock	Start Normal
		Operation

Clock Start (Clock Starts after VDD/ V DDQ Stable)

VDD/ V DDQ Stable (< +/- 0.1V DC per 50ns )

Fix High (or tied to VDDQ)

Document Number: 001-15271 Rev. *B Page 19 of 26

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