Cypress CY7C1383FV25 manual Ieee 1149.1 Serial Boundary Scan Jtag, TAP Controller State Diagram

Page 11

CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1381DV25/CY7C1383DV25 incorporates a serial boundary scan test access port (TAP). This part is fully compliant with 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V IO logic levels.

The CY7C1381DV25/CY7C1383DV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull up resistor. TDO may be left unconnected. Upon power up, the device will come up in a reset state, which will not interfere with the operation of the device.

TAP Controller State Diagram

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram).

Test Data-Out (TDO)

The TDO output ball is used to serially clock data out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.)

TAP Controller Block Diagram

0

1

0

TEST-LOGIC

RESET

0

RUN-TEST/

IDLE

1

SELECT

1

SELECT

 

DR-SCAN

 

IR-SCAN

 

 

0

 

 

0

 

1

 

 

1

 

 

CAPTURE-DR

 

CAPTURE-IR

 

 

0

 

 

0

 

SHIFT-DR

0

SHIFT-IR

 

 

1

 

 

1

 

EXIT1-DR

1

EXIT1-IR

 

 

 

 

0

 

 

0

 

PAUSE-DR

0

PAUSE-IR

 

 

1

 

 

1

 

0

 

 

0

 

 

EXIT2-DR

 

EXIT2-IR

 

 

1

 

 

1

 

UPDATE-DR

 

UPDATE-IR

 

1

0

 

1

0

1

0

1

0

 

 

 

 

 

 

 

 

 

 

 

Bypass Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Selection

 

 

 

 

 

 

 

 

 

 

2

 

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TDI

 

 

 

 

 

 

Instruction Register

 

 

 

 

S election

 

TDO

 

 

 

Circuitry

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Circuitr y

 

 

 

 

 

 

 

 

 

 

 

31

30

29

.

.

.

2

 

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Identification Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

x

.

.

.

.

.

2

 

 

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Boundary Scan Register

 

 

 

 

 

 

 

 

 

TCK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TAP CONTROLLER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TMS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This Reset does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.

The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.

TAP Registers

Registers are connected between the TDI and TDO balls and allow data to be scanned in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the TAP Controller Block Diagram. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.

Document #: 38-05547 Rev. *E

Page 11 of 28

[+] Feedback

Page 10 Page 12
Image 11
Page 10 Page 12
Contents Cypress Semiconductor Corporation FeaturesSelection Guide Functional Description 133 MHz 100 MHz UnitLogic Block Diagram CY7C1383DV25/CY7C1383FV25 3 1M x Logic Block Diagram CY7C1381DV25/CY7C1381FV25 3 512K xCY7C1383DV25 Mbit x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1381DV25 512K x Pin Configurations Ball BGA Pinout Pin Configurations Ball Fbga Pinout3 Chip Enable Byte write select inputs, active LOW. Qualified with Pin DefinitionsName Description Functional Overview = GND Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics AddressUsed Address Cycle DescriptionDQPC, Dqpa Truth Table for Read/Write 4Function CY7C1381DV25/CY7C1381FV25 DQPB, DqpaIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram TAP Instruction Set Bypass RegisterTAP Timing TAP AC Switching CharacteristicsScan Register Sizes 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Identification Register DefinitionsBit # Ball ID Identification CodesBall BGA Boundary Scan Order 13 Instruction Code DescriptionA11 Range Electrical CharacteristicsMaximum Ratings Operating RangePackage CapacitanceThermal Resistance AC Test Loads and WaveformsMin Max Switching CharacteristicsParameter Description 133 MHz 100 MHz Unit Min Read Cycle Timing Timing DiagramsAdsc Write Cycle Timing 25ADV Read/Write Cycle Timing 25, 27DON’T Care ZZ Mode Timing 29Ordering Information Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mm Package DiagramsBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Document History Issue Date Orig. Description of Change

CY7C1383DV25, CY7C1381FV25, CY7C1381DV25, CY7C1383FV25 specifications

Cypress Semiconductor's family of static random-access memory (SRAM) chips, including the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25, are designed for high-performance applications that require fast access times and low power consumption. These devices are often found in applications such as networking, telecommunications, and industrial control systems, where speed and reliability are paramount.

The CY7C1381FV25 and CY7C1381DV25 are single-port SRAMs, while the CY7C1383FV25 and CY7C1383DV25 are dual-port versions that allow for simultaneous read and write operations from two different controllers. This feature significantly enhances data throughput, making these devices ideal for high-bandwidth applications. The devices support asynchronous read and write operations, ensuring immediate data accessibility with minimal latency.

One of the key features of these SRAM chips is their fast access times, with read and write cycles as short as 10 nanoseconds. This speed makes them suitable for cache memory applications, where performance is critical. Furthermore, the devices are built on Cypress's advanced process technology, which enables them to achieve high density and low power consumption, ideal for battery-operated devices and systems where energy efficiency is crucial.

The power consumption characteristics also highlight their effectiveness in various applications. The active power consumption can be as low as 80mA, depending on the operation conditions, and the devices offer low standby power, further enhancing their suitability for low-power applications. Additionally, these chips incorporate power-saving features like sleep mode, allowing designers to minimize energy consumption in idle states.

In terms of reliability, Cypress employs rigorous quality control measures, ensuring that the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 meet stringent industry standards. They also feature an extended temperature range, which is vital for industrial applications that may experience harsh environmental conditions.

Overall, the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 SRAM chips are versatile, high-performance memory solutions. Their combination of fast access times, low power consumption, and reliability makes them an excellent choice for engineers and developers looking to implement high-speed memory in a variety of applications. Whether for a communication device or a sophisticated industrial control system, these Cypress SRAMs stand out in the market for their performance and efficiency.
Top Page Image Contents