Cypress CY7C1383DV25, CY7C1381FV25 manual Document History, Issue Date Orig. Description of Change

Page 28

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Document History Page

Document Title: CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/CY7C1383FV25, 18-Mbit (512K x 36/1M x 18)

Flow-Through SRAM

Document Number: 38-05547

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

 

 

 

 

**

254518

See ECN

RKF

New data sheet

 

 

 

 

 

*A

288531

See ECN

SYT

Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for

 

 

 

 

non-compliance with 1149.1

 

 

 

 

Removed 117Mhz Speed Bin

 

 

 

 

Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA

 

 

 

 

Packages

 

 

 

 

Added comment of ‘Pb-free BG packages availability’ below the Ordering

 

 

 

 

Information

*B

326078

See ECN

PCI

Address expansion pins/balls in the pinouts for all packages are modified as

 

 

 

 

per JEDEC standard

 

 

 

 

Added description on EXTEST Output Bus Tri-State

 

 

 

 

Changed description on the Tap Instruction Set Overview and Extest

 

 

 

 

Changed Device Width (23:18) for 119-BGA from 000001 to 101001

 

 

 

 

Added separate row for 165 -FBGA Device Width (23:18)

 

 

 

 

Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and

 

 

 

 

4.08 °C/W respectively

 

 

 

 

Changed ΘJA and ΘJc or BGA Package from 45 and 7 °C/W to 23.8 and 6.2

 

 

 

 

°C/W respectively

 

 

 

 

Changed ΘJA and ΘJc for FBGA Package from 46 and 3 °C/W to 20.7 and

 

 

 

 

4.0 °C/W respectively

 

 

 

 

Modified VOL, VOH test conditions

 

 

 

 

Removed comment of ‘Pb-free BG packages availability’ below the Ordering

 

 

 

 

Information

 

 

 

 

Updated Ordering Information Table

*C

416321

See ECN

NXR

Changed address of Cypress Semiconductor Corporation on Page# 1 from

 

 

 

 

“3901 North First Street” to “198 Champion Court”

 

 

 

 

Changed the description of IX from Input Load Current to Input Leakage

 

 

 

 

Current on page# 17

 

 

 

 

Changed the IX current values of MODE on page # 18 from –5 ∝A and 30 ∝A

 

 

 

 

to –30 ∝A and 5 ∝A

 

 

 

 

Changed the IX current values of ZZ on page # 18 from –30 ∝A and 5 ∝A

 

 

 

 

to –5 ∝A and 30 ∝A

 

 

 

 

Changed VIH < VDD to VIH < VDDon page # 18

 

 

 

 

Replaced Package Name column with Package Diagram in the Ordering

 

 

 

 

Information table

*D

475009

See ECN

VKN

Converted from Preliminary to Final.

 

 

 

 

Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND

 

 

 

 

Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP

 

 

 

 

AC Switching Characteristics table.

 

 

 

 

Updated the Ordering Information table.

*E

793579

See ECN

VKN

Added Part numbers CY7C1381FV25 and CY7C1383FV25

 

 

 

 

Added footnote# 3 regarding Chip Enable

 

 

 

 

Updated Ordering Information table

Document #: 38-05547 Rev. *E

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Contents Features Selection Guide Functional Description133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1381DV25/CY7C1381FV25 3 512K x Logic Block Diagram CY7C1383DV25/CY7C1383FV25 3 1M xCY7C1381DV25 512K x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1383DV25 Mbit x Pin Configurations Ball BGA Pinout Pin Configurations Ball Fbga Pinout3 Chip Enable Name Description Pin DefinitionsByte write select inputs, active LOW. Qualified with Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress = GNDAddress Cycle Description UsedTruth Table for Read/Write 4 Function CY7C1381DV25/CY7C1381FV25DQPB, Dqpa DQPC, DqpaTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP AC Switching Characteristics TAP Timing5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentIdentification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order 13Instruction Code Description Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms PackageParameter Description 133 MHz 100 MHz Unit Min Switching CharacteristicsMin Max Timing Diagrams Read Cycle TimingWrite Cycle Timing 25 AdscRead/Write Cycle Timing 25, 27 ADVZZ Mode Timing 29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1383DV25, CY7C1381FV25, CY7C1381DV25, CY7C1383FV25 specifications

Cypress Semiconductor's family of static random-access memory (SRAM) chips, including the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25, are designed for high-performance applications that require fast access times and low power consumption. These devices are often found in applications such as networking, telecommunications, and industrial control systems, where speed and reliability are paramount.

The CY7C1381FV25 and CY7C1381DV25 are single-port SRAMs, while the CY7C1383FV25 and CY7C1383DV25 are dual-port versions that allow for simultaneous read and write operations from two different controllers. This feature significantly enhances data throughput, making these devices ideal for high-bandwidth applications. The devices support asynchronous read and write operations, ensuring immediate data accessibility with minimal latency.

One of the key features of these SRAM chips is their fast access times, with read and write cycles as short as 10 nanoseconds. This speed makes them suitable for cache memory applications, where performance is critical. Furthermore, the devices are built on Cypress's advanced process technology, which enables them to achieve high density and low power consumption, ideal for battery-operated devices and systems where energy efficiency is crucial.

The power consumption characteristics also highlight their effectiveness in various applications. The active power consumption can be as low as 80mA, depending on the operation conditions, and the devices offer low standby power, further enhancing their suitability for low-power applications. Additionally, these chips incorporate power-saving features like sleep mode, allowing designers to minimize energy consumption in idle states.

In terms of reliability, Cypress employs rigorous quality control measures, ensuring that the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 meet stringent industry standards. They also feature an extended temperature range, which is vital for industrial applications that may experience harsh environmental conditions.

Overall, the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 SRAM chips are versatile, high-performance memory solutions. Their combination of fast access times, low power consumption, and reliability makes them an excellent choice for engineers and developers looking to implement high-speed memory in a variety of applications. Whether for a communication device or a sophisticated industrial control system, these Cypress SRAMs stand out in the market for their performance and efficiency.
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