Cypress manual Truth Table for Read/Write 4, Function CY7C1381DV25/CY7C1381FV25, DQPB, Dqpa

Page 10

CY7C1381DV25, CY7C1381FV25

CY7C1383DV25, CY7C1383FV25

Truth Table for Read/Write [4, 9]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Function (CY7C1381DV25/CY7C1381FV25)

 

GW

 

 

BWE

 

 

BWD

 

BWC

 

BWB

 

BWA

Read

 

H

 

 

H

 

 

X

 

X

 

X

 

X

Read

 

H

 

 

L

 

 

H

 

H

 

H

 

H

Write Byte A (DQA, DQPA)

 

H

 

 

L

 

 

H

 

H

 

H

 

L

Write Byte B (DQB, DQPB)

 

H

 

 

L

 

 

H

 

H

 

L

 

H

Write Bytes A, B (DQA, DQB, DQPA, DQPB)

 

H

 

 

L

 

 

H

 

H

 

L

 

L

Write Byte C (DQC, DQPC)

 

H

 

 

L

 

 

H

 

L

 

H

 

H

Write Bytes C, A (DQC, DQA, DQPC, DQPA)

 

H

 

 

L

 

 

H

 

L

 

H

 

L

Write Bytes C, B (DQC, DQB, DQPC, DQPB)

 

H

 

 

L

 

 

H

 

L

 

L

 

H

Write Bytes C, B, A (DQC, DQB, DQA, DQPC,

 

H

 

 

L

 

 

H

 

L

 

L

 

L

DQPB, DQPA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Byte D (DQD, DQPD)

 

H

 

 

L

 

 

L

 

H

 

H

 

H

Write Bytes D, A (DQD, DQA, DQPD, DQPA)

 

H

 

 

L

 

 

L

 

H

 

H

 

L

Write Bytes D, B (DQD, DQA, DQPD, DQPA)

 

H

 

 

L

 

 

L

 

H

 

L

 

H

Write Bytes D, B, A (DQD, DQB, DQA, DQPD,

 

H

 

 

L

 

 

L

 

H

 

L

 

L

DQPB, DQPA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, B (DQD, DQB, DQPD, DQPB)

 

H

 

 

L

 

 

L

 

L

 

H

 

H

Write Bytes D, B, A (DQD, DQC, DQA, DQPD,

 

H

 

 

L

 

 

L

 

L

 

H

 

L

DQPC, DQPA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write Bytes D, C, A (DQD, DQB, DQA, DQPD,

 

H

 

 

L

 

 

L

 

L

 

L

 

H

DQPB, DQPA)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write All Bytes

 

H

 

 

L

 

 

L

 

L

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Write All Bytes

 

L

 

 

X

 

 

X

 

X

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Truth Table for Read/Write [4, 9]

 

 

 

 

 

 

 

 

 

 

 

 

 

Function (CY7C1383DV25/CY7C1383FV25)

 

GW

 

 

BWE

 

 

BWB

 

BWA

Read

 

H

 

 

H

 

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

Read

 

H

 

 

L

 

 

H

 

H

 

 

 

 

 

 

 

 

 

 

 

Write Byte A – (DQA and DQPA)

 

H

 

 

L

 

 

H

 

L

Write Byte B – (DQB and DQPB)

 

H

 

 

L

 

 

L

 

H

Write All Bytes

 

H

 

 

L

 

 

L

 

L

 

 

 

 

 

 

 

 

 

 

 

Write All Bytes

 

L

 

 

X

 

 

X

 

X

 

 

 

 

 

 

 

 

 

 

 

 

 

Note

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

Document #: 38-05547 Rev. *E

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Contents 133 MHz 100 MHz Unit FeaturesSelection Guide Functional Description Cypress Semiconductor CorporationLogic Block Diagram CY7C1381DV25/CY7C1381FV25 3 512K x Logic Block Diagram CY7C1383DV25/CY7C1383FV25 3 1M xCY7C1381DV25 512K x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1383DV25 Mbit x Pin Configurations Ball BGA Pinout Pin Configurations Ball Fbga Pinout3 Chip Enable Name Description Pin DefinitionsByte write select inputs, active LOW. Qualified with Functional Overview Address Interleaved Burst Address Table Mode = Floating or VDDZZ Mode Electrical Characteristics = GNDAddress Cycle Description UsedDQPB, Dqpa Truth Table for Read/Write 4Function CY7C1381DV25/CY7C1381FV25 DQPC, DqpaTAP Controller Block Diagram TAP Controller State DiagramIeee 1149.1 Serial Boundary Scan Jtag Bypass Register TAP Instruction SetTAP AC Switching Characteristics TAP TimingIdentification Register Definitions 5V TAP AC Test Conditions5V TAP AC Output Load Equivalent Scan Register SizesInstruction Code Description Identification CodesBall BGA Boundary Scan Order 13 Bit # Ball IDA11 Operating Range Electrical CharacteristicsMaximum Ratings RangeAC Test Loads and Waveforms CapacitanceThermal Resistance PackageParameter Description 133 MHz 100 MHz Unit Min Switching CharacteristicsMin Max Timing Diagrams Read Cycle TimingWrite Cycle Timing 25 AdscRead/Write Cycle Timing 25, 27 ADVZZ Mode Timing 29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1383DV25, CY7C1381FV25, CY7C1381DV25, CY7C1383FV25 specifications

Cypress Semiconductor's family of static random-access memory (SRAM) chips, including the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25, are designed for high-performance applications that require fast access times and low power consumption. These devices are often found in applications such as networking, telecommunications, and industrial control systems, where speed and reliability are paramount.

The CY7C1381FV25 and CY7C1381DV25 are single-port SRAMs, while the CY7C1383FV25 and CY7C1383DV25 are dual-port versions that allow for simultaneous read and write operations from two different controllers. This feature significantly enhances data throughput, making these devices ideal for high-bandwidth applications. The devices support asynchronous read and write operations, ensuring immediate data accessibility with minimal latency.

One of the key features of these SRAM chips is their fast access times, with read and write cycles as short as 10 nanoseconds. This speed makes them suitable for cache memory applications, where performance is critical. Furthermore, the devices are built on Cypress's advanced process technology, which enables them to achieve high density and low power consumption, ideal for battery-operated devices and systems where energy efficiency is crucial.

The power consumption characteristics also highlight their effectiveness in various applications. The active power consumption can be as low as 80mA, depending on the operation conditions, and the devices offer low standby power, further enhancing their suitability for low-power applications. Additionally, these chips incorporate power-saving features like sleep mode, allowing designers to minimize energy consumption in idle states.

In terms of reliability, Cypress employs rigorous quality control measures, ensuring that the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 meet stringent industry standards. They also feature an extended temperature range, which is vital for industrial applications that may experience harsh environmental conditions.

Overall, the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 SRAM chips are versatile, high-performance memory solutions. Their combination of fast access times, low power consumption, and reliability makes them an excellent choice for engineers and developers looking to implement high-speed memory in a variety of applications. Whether for a communication device or a sophisticated industrial control system, these Cypress SRAMs stand out in the market for their performance and efficiency.
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