Cypress CY7C1383DV25, CY7C1381FV25 Interleaved Burst Address Table Mode = Floating or VDD, = Gnd

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CY7C1381DV25, CY7C1381FV25 CY7C1383DV25, CY7C1383FV25

and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all

asserted active, (2) ADSC is asserted LOW, (3) ADSP is deserted HIGH, and (4) the write input signals (GW, BWE, and BWX) indicate a write access. ADSC is ignored if ADSP is active LOW.

The addresses presented are loaded into the address register and the burst counter, the control logic, or both, and delivered to the memory core. The information presented to DQX will be written into the specified address location. Byte writes are allowed. All IOs are tri-stated when a write is detected, even a byte write. Since this is a common IO device, the asynchronous OE input signal must be deasserted and the IOs must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1381DV25/CY7C1383DV25/CY7C1381FV25/ CY7C1383FV25 provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation sleep mode. Two clock cycles are required to enter into or exit from this sleep mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the sleep mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the sleep mode. CE1, CE2, CE3 [2], ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table (MODE = Floating or VDD)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

00

11

10

 

 

 

 

10

11

00

01

 

 

 

 

11

10

01

00

 

 

 

 

Linear Burst

Address

Table (MODE

= GND)

First

Second

Third

Fourth

Address

Address

Address

Address

A1: A0

A1: A0

A1: A0

A1: A0

00

01

10

11

 

 

 

 

01

10

11

00

 

 

 

 

10

11

00

01

 

 

 

 

11

00

01

10

 

 

 

 

ZZ Mode Electrical Characteristics

Parameter

Description

Test Conditions

Min.

Max.

Unit

IDDZZ

Sleep mode standby current

ZZ > VDD – 0.2V

 

80

mA

tZZS

Device operation to ZZ

ZZ > VDD – 0.2V

 

2tCYC

ns

tZZREC

ZZ recovery time

ZZ < 0.2V

2tCYC

 

ns

tZZI

ZZ active to sleep current

This parameter is sampled

 

2tCYC

ns

tRZZI

ZZ Inactive to exit sleep current

This parameter is sampled

0

 

ns

Document #: 38-05547 Rev. *E

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Contents Features Selection Guide Functional Description133 MHz 100 MHz Unit Cypress Semiconductor CorporationLogic Block Diagram CY7C1381DV25/CY7C1381FV25 3 512K x Logic Block Diagram CY7C1383DV25/CY7C1383FV25 3 1M xCY7C1383DV25 Mbit x Pin Configurations Pin Tqfp Pinout 3 Chip EnableCY7C1381DV25 512K x Pin Configurations Ball BGA Pinout Pin Configurations Ball Fbga Pinout3 Chip Enable Byte write select inputs, active LOW. Qualified with Pin DefinitionsName Description Functional Overview Interleaved Burst Address Table Mode = Floating or VDD ZZ Mode Electrical CharacteristicsAddress = GNDAddress Cycle Description UsedTruth Table for Read/Write 4 Function CY7C1381DV25/CY7C1381FV25DQPB, Dqpa DQPC, DqpaIeee 1149.1 Serial Boundary Scan Jtag TAP Controller State DiagramTAP Controller Block Diagram Bypass Register TAP Instruction SetTAP AC Switching Characteristics TAP Timing5V TAP AC Test Conditions 5V TAP AC Output Load EquivalentIdentification Register Definitions Scan Register SizesIdentification Codes Ball BGA Boundary Scan Order 13Instruction Code Description Bit # Ball IDA11 Electrical Characteristics Maximum RatingsOperating Range RangeCapacitance Thermal ResistanceAC Test Loads and Waveforms PackageMin Max Switching CharacteristicsParameter Description 133 MHz 100 MHz Unit Min Timing Diagrams Read Cycle TimingWrite Cycle Timing 25 AdscRead/Write Cycle Timing 25, 27 ADVZZ Mode Timing 29 DON’T CareOrdering Information Package Diagrams Pin Thin Plastic Quad Flat pack 14 x 20 x 1.4 mmBall BGA 14 x 22 x 2.4 mm Soldernotespad Type NON-SOLDER Mask Defined Nsmd Issue Date Orig. Description of Change Document History

CY7C1383DV25, CY7C1381FV25, CY7C1381DV25, CY7C1383FV25 specifications

Cypress Semiconductor's family of static random-access memory (SRAM) chips, including the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25, are designed for high-performance applications that require fast access times and low power consumption. These devices are often found in applications such as networking, telecommunications, and industrial control systems, where speed and reliability are paramount.

The CY7C1381FV25 and CY7C1381DV25 are single-port SRAMs, while the CY7C1383FV25 and CY7C1383DV25 are dual-port versions that allow for simultaneous read and write operations from two different controllers. This feature significantly enhances data throughput, making these devices ideal for high-bandwidth applications. The devices support asynchronous read and write operations, ensuring immediate data accessibility with minimal latency.

One of the key features of these SRAM chips is their fast access times, with read and write cycles as short as 10 nanoseconds. This speed makes them suitable for cache memory applications, where performance is critical. Furthermore, the devices are built on Cypress's advanced process technology, which enables them to achieve high density and low power consumption, ideal for battery-operated devices and systems where energy efficiency is crucial.

The power consumption characteristics also highlight their effectiveness in various applications. The active power consumption can be as low as 80mA, depending on the operation conditions, and the devices offer low standby power, further enhancing their suitability for low-power applications. Additionally, these chips incorporate power-saving features like sleep mode, allowing designers to minimize energy consumption in idle states.

In terms of reliability, Cypress employs rigorous quality control measures, ensuring that the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 meet stringent industry standards. They also feature an extended temperature range, which is vital for industrial applications that may experience harsh environmental conditions.

Overall, the CY7C1381FV25, CY7C1383DV25, CY7C1381DV25, and CY7C1383FV25 SRAM chips are versatile, high-performance memory solutions. Their combination of fast access times, low power consumption, and reliability makes them an excellent choice for engineers and developers looking to implement high-speed memory in a variety of applications. Whether for a communication device or a sophisticated industrial control system, these Cypress SRAMs stand out in the market for their performance and efficiency.
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