Cypress CY7C1426JV18 Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1411JV18 4M x

Page 4

CY7C1411JV18, CY7C1426JV18

CY7C1413JV18, CY7C1415JV18

Pin Configuration

The pin configuration for CY7C1411JV18, CY7C1413JV18, and CY7C1415JV18 follows. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1411JV18 (4M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

1

NC/144M

A

A

CQ

CQ

WPS

NWS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q3

NWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D3

D

NC

D4

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q4

VDDQ

VSS

VSS

VSS

VDDQ

NC

D2

Q2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D5

Q5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q1

D1

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q6

D6

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D0

N

NC

D7

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q7

A

A

C

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1426JV18 (4M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

NC

NC/144M

A

A

CQ

CQ

WPS

K

RPS

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

Q4

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

NC

D4

D

NC

D5

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

Q5

VDDQ

VSS

VSS

VSS

VDDQ

NC

D3

Q3

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

D6

Q6

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

Q2

D2

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

Q7

D7

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

Q1

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

D1

N

NC

D8

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

Q8

A

A

C

A

A

NC

D0

Q0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Note

1. NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-12557 Rev. *C

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Contents Features Configurations Functional Description Selection GuideLogic Block Diagram CY7C1426JV18 Logic Block Diagram CY7C1411JV18Doff Logic Block Diagram CY7C1413JV18 Logic Block Diagram CY7C1415JV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1411JV18 4M x CY7C1426JV18 4M xWPS BWS CY7C1413JV18 2M xCY7C1415JV18 1M x Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced With Respect to TDO for JtagFunctional Overview Application Example Depth ExpansionProgrammable Impedance Echo ClocksTruth Table Write Cycle DescriptionsOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsScan Register Sizes Identification Register DefinitionsInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence Power Up Sequence in QDR-II SramDLL Constraints DC Electrical Characteristics Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics HighLOW DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 27, 28Ordering Information 200 Package Diagram Ball Fbga 15 x 17 x 1.40 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions