Cypress CY7C1411JV18, CY7C1426JV18, CY7C1415JV18, CY7C1413JV18 manual AC Electrical Characteristics

Page 21

CY7C1411JV18, CY7C1426JV18

CY7C1413JV18, CY7C1415JV18

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range [14]

Parameter

Description

Test Conditions

 

Min

Typ

Max

Unit

ISB1

Automatic Power Down

Max VDD,

300 MHz

(x8)

 

 

350

mA

 

Current

Both Ports Deselected,

 

 

 

 

 

 

 

 

(x9)

 

 

350

 

 

 

VIN VIH or VIN VIL

 

 

 

 

 

 

 

(x18)

 

 

355

 

 

 

f = fMAX = 1/tCYC, Inputs

 

 

 

 

 

 

Static

 

(x36)

 

 

395

 

 

 

 

250 MHz

(x8)

 

 

355

mA

 

 

 

 

(x9)

 

 

355

 

 

 

 

 

(x18)

 

 

355

 

 

 

 

 

(x36)

 

 

370

 

 

 

 

200 MHz

(x8)

 

 

300

mA

 

 

 

 

(x9)

 

 

300

 

 

 

 

 

(x18)

 

 

300

 

 

 

 

 

(x36)

 

 

300

 

AC Electrical Characteristics

Over the Operating Range [13]

Parameter

Description

Test Conditions

Min

Typ

Max

Unit

VIH

Input HIGH Voltage

 

VREF + 0.2

V

VIL

Input LOW Voltage

 

VREF – 0.2

V

Document Number: 001-12557 Rev. *C

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1411JV18 Logic Block Diagram CY7C1426JV18Doff Logic Block Diagram CY7C1415JV18 Logic Block Diagram CY7C1413JV18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1411JV18 4M x CY7C1426JV18 4M xCY7C1413JV18 2M x WPS BWSCY7C1415JV18 1M x Pin Name Pin Description Pin DefinitionsPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceIs Referenced With Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksWrite Cycle Descriptions Truth TableOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTAP Timing and Test Conditions TAP AC Switching CharacteristicsIdentification Register Definitions Scan Register SizesInstruction Codes Bit # Bump ID Boundary Scan OrderPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitHigh Switching CharacteristicsLOW DLL TimingRead/Write/Deselect Sequence 27, 28 Switching WaveformsOrdering Information 200 Ball Fbga 15 x 17 x 1.40 mm Package DiagramWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal Information