Cypress CY7C1426JV18, CY7C1411JV18, CY7C1415JV18, CY7C1413JV18 manual Functional Overview

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CY7C1411JV18, CY7C1426JV18 CY7C1413JV18, CY7C1415JV18

Functional Overview

The CY7C1411JV18, CY7C1426JV18, CY7C1413JV18, and CY7C1415JV18 are synchronous pipelined burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR-II completely eliminates the need to “turn around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1411JV18, four 9-bit data transfers in the case of CY7C1426JV18, four 18-bit data transfers in the case of CY7C1413JV18, and four 36-bit transfers data in the case of CY7C1415JV18 in two clock cycles.

This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then device behaves in QDR-I mode with a read latency of one clock cycle.

Accesses for both ports are initiated on the positive input clock

(K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is refer- enced to the output clocks (C and C or K and K when in single clock mode).

All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode).

All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K).

CY7C1413JV18 is described in the following sections. The same basic descriptions apply to CY7C1411JV18, CY7C1426JV18, and CY7C1415JV18.

Read Operations

The CY7C1413JV18 is organized internally as four arrays of 512K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address presented to address inputs are stored in the read address register. Following the next K clock rise, the corre- sponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subse- quent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data is valid 0.45 ns from the rising edge of the output clock (C or C, or K or K when in single clock mode). To maintain the internal logic, each read access must be allowed to complete. Each read access consists of four 18-bit data words and takes two clock cycles to complete. Therefore, read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device ignores the second read request. Read accesses can be initiated on every other K clock rise. Doing so pipelines the data flow such that data is transferred out of the device on every

rising edge of the output clocks (C and C, or K and K when in single clock mode).

When the read port is deselected, the CY7C1413JV18 first completes the pending read transactions. Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive output clock (C). This enables a transition between devices without the insertion of wait states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the information presented to D[17:0] is also stored into the write data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, write accesses to the device cannot be initiated on two consecutive K clock rises. The internal logic of the device ignores the second write request. Initiate write access on every other rising edge of the positive input clock (K). Doing so pipelines the data flow such that 18 bits of data transfers into the device on every rising edge of the input clocks (K and K).

When deselected, the write port ignores all inputs after the pending write operations have been completed.

Byte Write Operations

Byte write operations are supported by the CY7C1413JV18. A write operation is initiated as described in the Write Operations section. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the byte write select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the byte write select input during the data portion of a write enables the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation.

Single Clock Mode

The CY7C1411JV18 can be used with a single clock that controls both the input and output registers. In this mode the device recognizes only a single pair of input clock (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remains the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation.

Concurrent Transactions

The read and write ports on the CY7C1413JV18 operates independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM delivers the most recent information associated with the specified address location. This

Document Number: 001-12557 Rev. *C

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Contents Features ConfigurationsFunctional Description Selection GuideDoff Logic Block Diagram CY7C1411JV18Logic Block Diagram CY7C1426JV18 Logic Block Diagram CY7C1413JV18 Logic Block Diagram CY7C1415JV18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1411JV18 4M x CY7C1426JV18 4M xCY7C1415JV18 1M x CY7C1413JV18 2M xWPS BWS Pin Definitions Pin Name Pin DescriptionPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceIs Referenced With Respect to TDO for JtagFunctional Overview Application Example Depth ExpansionProgrammable Impedance Echo ClocksTruth Table Write Cycle DescriptionsOperation CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Boundary Scan Order Bit # Bump IDDLL Constraints Power Up Sequence in QDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Capacitance Thermal ResistanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics HighLOW DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 27, 28Ordering Information 200 Package Diagram Ball Fbga 15 x 17 x 1.40 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

CY7C1413JV18, CY7C1426JV18, CY7C1411JV18, CY7C1415JV18 specifications

Cypress Semiconductor, known for its innovative memory solutions, offers a range of high-performance SRAM products suitable for a variety of applications. Among these are the CY7C1415JV18, CY7C1411JV18, CY7C1426JV18, and CY7C1413JV18, which feature advanced technologies and robust performance characteristics.

The CY7C1415JV18 is a 4-Mbit high-speed asynchronous SRAM. Designed for applications requiring fast data access, it boasts a maximum access time of just 10 ns. This product operates at a supply voltage of 1.8V, making it ideal for low-power systems. It supports a simple interface, allowing for easy integration into various digital systems. Enhanced data integrity is assured through support for write cycles and concurrent read operations, making it suitable for high-demand environments.

The CY7C1411JV18 is a 2-Mbit synchronous SRAM that offers high speed and low latency. Its access time is optimized for high-performance applications, reaching speeds of up to 10 ns as well. The device is designed with a flexible interface that accommodates both burst and non-burst operations, increasing data throughput for memory-intensive tasks. Like its counterparts, it operates on a low voltage, ensuring minimal power consumption.

Next, the CY7C1426JV18 also belongs to Cypress's high-performance SRAM family, providing 2-Mbit storage capacity with excellent read and write performance characteristics. This SRAM features an advanced design that supports pipelined operations, allowing multiple memory accesses to occur simultaneously. This feature effectively maximizes data transmission rates, making it particularly appealing for applications needing rapid data processing.

Finally, the CY7C1413JV18 offers 1-Mbit of SRAM capacity optimized for speed and efficiency. With an access time of 9 ns, it is among the fastest products in its category. The device features advanced functionalities enabling compatibility with various hardware configurations, thus facilitating its use in a wide array of embedded systems.

All these SRAM devices feature low power consumption, making them suitable for battery-operated devices and energy-efficient applications. Their ability to operate at lower voltages while maintaining high performance is a key characteristic that aligns with modern design requirements. The combination of speed, low power, and flexibility makes the CY7C1415JV18, CY7C1411JV18, CY7C1426JV18, and CY7C1413JV18 highly sought after in industries ranging from telecommunications to consumer electronics, solidifying Cypress's reputation as a leader in memory solutions.
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