Cypress CY7C1415JV18, CY7C1426JV18, CY7C1411JV18 manual Pin Definitions, Pin Name Pin Description

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CY7C1411JV18, CY7C1426JV18

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1413JV18, CY7C1415JV18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

Pin Description

 

 

D[x:0]

Input-

Data Input Signals. Sampled on the rising edge of K and

 

clocks when valid write operations are active.

 

K

 

 

 

 

 

 

Synchronous

CY7C1411JV18 − D[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1426JV18 − D[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1413JV18 − D[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1415JV18 − D[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Write Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a

 

 

WPS

 

 

 

 

 

 

Synchronous

write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].

 

 

 

 

 

0,

Input-

Nibble Write Select 0, 1 − Active LOW (CY7C1411JV18 Only). Sampled on the rising edge of the K

 

 

NWS

 

 

NWS1,

Synchronous

and K clocks when write operations are active. Used to select which nibble is written into the device during

 

 

 

 

 

 

 

the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].

 

 

 

 

 

 

 

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select

 

 

 

 

 

 

 

ignores the corresponding nibble of data and it is not written into the device.

 

 

 

 

0,

Input-

Byte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and

 

 

clocks when

 

 

BWS

K

 

 

BWS1,

Synchronous

write operations are active. Used to select which byte is written into the device during the current portion

 

 

BWS2,

 

of the write operations. Bytes not written remain unaltered.

 

 

BWS3

 

CY7C1426JV18 − BWS0

controls D[8:0]

 

 

 

 

 

 

 

CY7C1413JV18 − BWS0

controls D[8:0] and

BWS

1 controls D

[17:9].

 

 

 

 

 

 

 

 

 

 

CY7C1415JV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls

 

 

 

 

 

 

 

D[35:27].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

 

 

 

 

 

 

 

ignores the corresponding byte of data and it is not written into the device.

 

 

A

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These

 

 

 

 

 

 

Synchronous

address inputs are multiplexed for both read and write operations. Internally, the device is organized as

 

 

 

 

 

 

 

4M x 8 (4 arrays each of 1M x 8) for CY7C1411JV18, 4M x 9 (4 arrays each of 1M x 9) for CY7C1426JV18,

 

 

 

 

 

 

 

2M x 18 (4 arrays each of 512K x 18) for CY7C1413JV18 and 1M x 36 (4 arrays each of 256K x 36) for

 

 

 

 

 

 

 

CY7C1415JV18. Therefore, only 20 address inputs are needed to access the entire memory array of

 

 

 

 

 

 

 

CY7C1411JV18 and CY7C1426JV18, 19 address inputs for CY7C1413JV18 and 18 address inputs for

 

 

 

 

 

 

 

CY7C1415JV18. These inputs are ignored when the appropriate port is deselected.

 

 

Q[x:0]

Outputs-

Data Output Signals. These pins drive out the requested data when the read operation is active. Valid

 

 

 

 

 

 

Synchronous

data is driven out on the rising edge of the C and C clocks during read operations or K and K, when in

 

 

 

 

 

 

 

single clock mode. On deselecting the read port, Q[x:0] are automatically tri-stated.

 

 

 

 

 

 

 

CY7C1411JV18 − Q[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1426JV18 − Q[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1413JV18 − Q[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1415JV18 − Q[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input-

Read Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a

 

 

RPS

 

 

 

 

 

 

Synchronous

read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is

 

 

 

 

 

 

 

allowed to complete and the output drivers are automatically tri-stated following the next rising edge of

 

 

 

 

 

 

 

the C clock. Each read access consists of a burst of four sequential transfers.

 

CInput Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.

CInput Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details.

K

Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

 

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

 

edge of K.

KInput Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode.

Document Number: 001-12557 Rev. *C

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1411JV18 Logic Block Diagram CY7C1426JV18Doff Logic Block Diagram CY7C1413JV18 Logic Block Diagram CY7C1415JV18CY7C1411JV18 4M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1426JV18 4M xCY7C1413JV18 2M x WPS BWSCY7C1415JV18 1M x Pin Definitions Pin Name Pin DescriptionIs Referenced With Respect to Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview Programmable Impedance Application ExampleDepth Expansion Echo ClocksOperation Truth TableWrite Cycle Descriptions CommentsBWS0 Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Controller Block Diagram TAP Electrical CharacteristicsTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Boundary Scan Order Bit # Bump IDPower Up Sequence in QDR-II Sram Power Up SequenceDLL Constraints Electrical Characteristics DC Electrical CharacteristicsMaximum Ratings AC Electrical Characteristics Parameter Description Test Conditions Max Unit CapacitanceThermal Resistance Parameter Description Test Conditions Fbga UnitLOW Switching CharacteristicsHigh DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 27, 28Ordering Information 200 Package Diagram Ball Fbga 15 x 17 x 1.40 mmSales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC Solutions

CY7C1413JV18, CY7C1426JV18, CY7C1411JV18, CY7C1415JV18 specifications

Cypress Semiconductor, known for its innovative memory solutions, offers a range of high-performance SRAM products suitable for a variety of applications. Among these are the CY7C1415JV18, CY7C1411JV18, CY7C1426JV18, and CY7C1413JV18, which feature advanced technologies and robust performance characteristics.

The CY7C1415JV18 is a 4-Mbit high-speed asynchronous SRAM. Designed for applications requiring fast data access, it boasts a maximum access time of just 10 ns. This product operates at a supply voltage of 1.8V, making it ideal for low-power systems. It supports a simple interface, allowing for easy integration into various digital systems. Enhanced data integrity is assured through support for write cycles and concurrent read operations, making it suitable for high-demand environments.

The CY7C1411JV18 is a 2-Mbit synchronous SRAM that offers high speed and low latency. Its access time is optimized for high-performance applications, reaching speeds of up to 10 ns as well. The device is designed with a flexible interface that accommodates both burst and non-burst operations, increasing data throughput for memory-intensive tasks. Like its counterparts, it operates on a low voltage, ensuring minimal power consumption.

Next, the CY7C1426JV18 also belongs to Cypress's high-performance SRAM family, providing 2-Mbit storage capacity with excellent read and write performance characteristics. This SRAM features an advanced design that supports pipelined operations, allowing multiple memory accesses to occur simultaneously. This feature effectively maximizes data transmission rates, making it particularly appealing for applications needing rapid data processing.

Finally, the CY7C1413JV18 offers 1-Mbit of SRAM capacity optimized for speed and efficiency. With an access time of 9 ns, it is among the fastest products in its category. The device features advanced functionalities enabling compatibility with various hardware configurations, thus facilitating its use in a wide array of embedded systems.

All these SRAM devices feature low power consumption, making them suitable for battery-operated devices and energy-efficient applications. Their ability to operate at lower voltages while maintaining high performance is a key characteristic that aligns with modern design requirements. The combination of speed, low power, and flexibility makes the CY7C1415JV18, CY7C1411JV18, CY7C1426JV18, and CY7C1413JV18 highly sought after in industries ranging from telecommunications to consumer electronics, solidifying Cypress's reputation as a leader in memory solutions.
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