Cypress CY7C1418AV18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

Page 17

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Identification Register Definitions

Instruction Field

 

Value

 

Description

CY7C1416AV18

CY7C1427AV18

CY7C1418AV18

CY7C1420AV18

 

 

Revision Number

000

000

000

000

Version number.

(31:29)

 

 

 

 

 

Cypress Device ID

11010100010000111

11010100010001111

11010100010010111

11010100010100111

Defines the type of

(28:12)

 

 

 

 

SRAM.

Cypress JEDEC ID

00000110100

00000110100

00000110100

00000110100

Allows unique

(11:1)

 

 

 

 

identification of

 

 

 

 

 

SRAM vendor.

ID Register

1

1

1

1

Indicates the

Presence (0)

 

 

 

 

presence of an ID

 

 

 

 

 

register.

Scan Register Sizes

Register Name

Bit Size

Instruction

3

 

 

Bypass

1

 

 

ID

32

 

 

Boundary Scan

109

 

 

Instruction Codes

Instruction

Code

Description

EXTEST

000

Captures the input and output ring contents.

 

 

 

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.

 

 

This operation does not affect SRAM operation.

SAMPLE Z

010

Captures the input and output contents. Places the boundary scan register between TDI and

 

 

TDO. Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

 

 

 

SAMPLE/PRELOAD

100

Captures the input and output ring contents. Places the boundary scan register between TDI

 

 

and TDO. Does not affect the SRAM operation.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

 

 

 

RESERVED

110

Do Not Use: This instruction is reserved for future use.

 

 

 

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM

 

 

operation.

Document Number: 38-05616 Rev. *F

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1427AV18 Logic Block Diagram CY7C1416AV18Doff CLKBWS Logic Block Diagram CY7C1418AV18Logic Block Diagram CY7C1420AV18 Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1416AV18 4M x CY7C1427AV18 4M xCY7C1420AV18 1M x CY7C1418AV18 2M xSynchronous Read or Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksNWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Clock Rise or K/K in single Clock mode to Data Valid NOP Switching WaveformsRead NOP Write ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramOirg. Submission Date Description Of Change Document HistoryECN Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/AESA Pyrs