Cypress CY7C1416AV18, CY7C1427AV18 manual CY7C1418AV18 2M x, CY7C1420AV18 1M x

Page 5

CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Pin Configuration (continued)

The pin configuration for CY7C1416AV18, CY7C1427AV18, CY7C1418AV18, and CY7C1420AV18 follow. [1]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1418AV18 (2M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

NC/72M

A

CQ

R/W

BWS1

K

NC/144M

LD

A

A

CQ

B

NC

DQ9

NC

A

NC/288M

K

0

A

NC

NC

DQ8

BWS

C

NC

NC

NC

VSS

A

A0

A

VSS

NC

DQ7

NC

D

NC

NC

DQ10

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ11

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ6

F

NC

DQ12

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

NC

DQ13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ4

NC

K

NC

NC

DQ14

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ3

L

NC

DQ15

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

DQ1

NC

N

NC

NC

DQ16

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ17

A

A

C

A

A

NC

NC

DQ0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

CY7C1420AV18 (1M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

A

CQ

R/W

BWS2

K

BWS1

LD

A

NC/72M

CQ

B

NC

DQ27

DQ18

A

3

K

0

A

NC

NC

DQ8

BWS

BWS

C

NC

NC

DQ28

VSS

A

A0

A

VSS

NC

DQ17

DQ7

D

NC

DQ29

DQ19

VSS

VSS

VSS

VSS

VSS

NC

NC

DQ16

E

NC

NC

DQ20

VDDQ

VSS

VSS

VSS

VDDQ

NC

DQ15

DQ6

F

NC

DQ30

DQ21

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

DQ31

DQ22

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ14

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

DQ32

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ13

DQ4

K

NC

NC

DQ23

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ12

DQ3

L

NC

DQ33

DQ24

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

DQ34

VSS

VSS

VSS

VSS

VSS

NC

DQ11

DQ1

N

NC

DQ35

DQ25

VSS

A

A

A

VSS

NC

NC

DQ10

P

NC

NC

DQ26

A

A

C

A

A

NC

DQ9

DQ0

R

TDO

TCK

A

A

A

A

A

A

TMS

TDI

C

Document Number: 38-05616 Rev. *F

Page 5 of 31

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1427AV18 Logic Block Diagram CY7C1416AV18Doff CLKBWS Logic Block Diagram CY7C1418AV18Logic Block Diagram CY7C1420AV18 Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1416AV18 4M x CY7C1427AV18 4M xCY7C1420AV18 1M x CY7C1418AV18 2M xSynchronous Read or Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksNWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Clock Rise or K/K in single Clock mode to Data Valid NOP Switching WaveformsRead NOP Write ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramOirg. Submission Date Description Of Change Document HistoryECN Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/AESA Pyrs