Cypress CY7C1418AV18, CY7C1416AV18, CY7C1420AV18 manual Package Diagram, Ball Fbga 15 x 17 x 1.4 mm

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CY7C1416AV18, CY7C1427AV18

CY7C1418AV18, CY7C1420AV18

Package Diagram

Figure 6. 165-ball FBGA (15 x 17 x 1.4 mm), 51-85195

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Document Number: 38-05616 Rev. *F

Page 29 of 31

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1427AV18 Logic Block Diagram CY7C1416AV18Doff CLKBWS Logic Block Diagram CY7C1418AV18Logic Block Diagram CY7C1420AV18 Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1416AV18 4M x CY7C1427AV18 4M xCY7C1420AV18 1M x CY7C1418AV18 2M xSynchronous Read or Write Input. When Pin DefinitionsPin Name Pin Description Power Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceReferenced with Respect to TDO for JtagFunctional Overview Depth Expansion Application ExampleProgrammable Impedance Echo ClocksNWS0 NWS1 Write Cycle DescriptionsBWS0 BWS1 BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram TAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit # Bump ID Boundary Scan OrderDLL Constraints Power Up Sequence in DDR-II SramPower Up Sequence Maximum Ratings Electrical CharacteristicsDC Electrical Characteristics AC Electrical Characteristics Thermal Resistance CapacitanceParameter Description Test Conditions Max Unit Parameter Description Test Conditions Fbga UnitSwitching Characteristics Clock Rise or K/K in single Clock mode to Data Valid NOP Switching WaveformsRead NOP Write ReadOrdering Information 250 167 Ball Fbga 15 x 17 x 1.4 mm Package DiagramOirg. Submission Date Description Of Change Document HistoryECN Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationVKN/AESA Pyrs